Abstract: An electronic package (200) comprises a substrate (201), a first carrier layer arrangement (211) adapted to dissipate heat from at least one chip (217) mounted thereon, and a heat exchanger (221) mounted on the first carrier layer arrangement. The first carrier layer arrangement comprises at least one internal microchannel (213), which is fluidically interconnected with the heat exchanger (221) though an inlet (215) and an outlet (219). The heat exchange further comprises a pump (223) controlling fluid flow through the microchannel (213). The package may further comprise a stack of carrier layer arrangements (211), each of which may have one or more chips (217) mounted thereon.

Abstract: The present invention provides a method for straining a semiconductor wafer, the method comprising: providing a semiconductor wafer, the semiconductor wafer having a first wafer surface and a second wafer surface arranged substantially opposite the first wafer surface; providing a substrate, the substrate having a substrate surface; adhering the first wafer surface to the substrate surface, thereby connecting the semiconductor wafer to the substrate and forming a wafer substrate unit; heating the semiconductor wafer and the substrate to a first temperature; and cooling the wafer substrate unit to a second temperature lower than the first temperature; thereby straining and bending the semiconductor wafer. The present invention further provides a wafer substrate unit.

Abstract: A method for micro-component self-assembly is disclosed. An embodiment self-assembly method provides a substrate with an interconnect, and a micro-device having a corresponding interconnect that is arranged for engagement with the interconnect of the substrate during the self-assembly process. A method for fabricating a micro-device for micro-component self-assembly with a substrate and a method for fabricating a substrate for micro-component self-assembly with a micro-device are also disclosed.

Abstract: An interconnect structure for interconnecting an integrated circuit (IC) chip to a next level, a method of fabricating the interconnect at wafer level, and a method of interconnecting an integrated circuit (IC) chip to the next level. The interconnect structure comprises one or more planar micro-spring elements formed on a packaging surface of the chip and connected to an interconnection pad; wherein the interconnection pad is resiliently moveable horizontally and vertically with respect to the surface of the chip. A layer of solder is preferably electroplated onto the interconnection pad to provide interconnection to the next level. In a variation of the interconnect structure, a metal column is fabricated onto the interconnection pad prior to electroplating the solder layer.