Abstract: The present disclosure relates to a Wafer-Level-Packaged (WLP) Bulk Acoustic Wave (BAW) device that includes a BAW resonator, a WLP enclosure, and a surface mount connection structure. The BAW resonator includes a piezoelectric layer with an opening and a bottom electrode lead underneath the piezoelectric layer, such that a portion of the bottom electrode lead is exposed through the opening of the piezoelectric layer. The WLP enclosure includes a cap and an outer wall that extends from the cap toward the piezoelectric layer to form a cavity. The opening of the piezoelectric layer is outside the cavity. The surface mount connection structure covers a portion of a top surface of the cap and extends continuously over a side portion of the WLP enclosure and to the exposed portion of the bottom electrode lead through the opening of the piezoelectric layer.

Abstract: Stealth-dicing-compatible devices and methods to prevent acoustic backside reflections on acoustic wave devices are disclosed. An acoustic wave device comprises a substrate having opposing top and bottom surfaces, where a first portion of the bottom surface has a higher roughness than a second portion of the bottom surface, and an acoustic resonator over the top surface of the substrate. The acoustic resonator comprises a piezoelectric layer having opposing top and bottom surfaces and a plurality of electrodes, at least some of which are disposed on the top surface of the piezoelectric layer. The first portion of the bottom surface of the substrate is below and opposite from the acoustic resonator, and the second portion of the bottom surface of the substrate is not located below and opposite from the acoustic resonator. Multiple first portions, each separated from the other by second portions, may exist.

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for formation of a dielectric with a smooth surface. In one embodiment, a method includes providing a dielectric with first and second surfaces, a conductive feature formed on the first surface, and a laminate applied to the second surface, curing the second surface while the laminate remains applied, and removing the laminate. Other embodiments may be described and/or claimed.

Abstract: The present disclosure relates to a Wafer-Level-Packaged (WLP) Bulk Acoustic Wave (BAW) device that includes a BAW resonator, a WLP enclosure, and a surface mount connection structure. The BAW resonator includes a piezoelectric layer with an opening and a bottom electrode lead underneath the piezoelectric layer, such that a portion of the bottom electrode lead is exposed through the opening of the piezoelectric layer. The WLP enclosure includes a cap and an outer wall that extends from the cap toward the piezoelectric layer to form a cavity. The opening of the piezoelectric layer is outside the cavity. The surface mount connection structure covers a portion of a top surface of the cap and extends continuously over a side portion of the WLP enclosure and to the exposed portion of the bottom electrode lead through the opening of the piezoelectric layer.

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a CVD dielectric material on a package dielectric material, and then forming a conductive material on the CVD dielectric material.

Abstract: Stealth-dicing-compatible devices and methods to prevent acoustic backside reflections on acoustic wave devices are disclosed. An acoustic wave device comprises a substrate having opposing top and bottom surfaces, where a first portion of the bottom surface has a higher roughness than a second portion of the bottom surface, and an acoustic resonator over the top surface of the substrate. The acoustic resonator comprises a piezoelectric layer having opposing top and bottom surfaces and a plurality of electrodes, at least some of which are disposed on the top surface of the piezoelectric layer. The first portion of the bottom surface of the substrate is below and opposite from the acoustic resonator, and the second portion of the bottom surface of the substrate is not located below and opposite from the acoustic resonator. Multiple first portions, each separated from the other by second portions, may exist.

Abstract: Bumpless build-up layer (BBUL) semiconductor packages with ultra-thin dielectric layers are described. For example, an apparatus includes a semiconductor die including an integrated circuit having a plurality of external conductive bumps. A semiconductor package houses the semiconductor die. The semiconductor package includes a dielectric layer disposed above the plurality of external conductive bumps. A conductive via is disposed in the dielectric layer and coupled to one of the plurality of conductive bumps. A conductive line is disposed on the dielectric layer and coupled to the conductive via.

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for formation of a dielectric with a smooth surface. In one embodiment, a method includes providing a dielectric with first and second surfaces, a conductive feature formed on the first surface, and a laminate applied to the second surface, curing the second surface while the laminate remains applied, and removing the laminate. Other embodiments may be described and/or claimed.

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a CVD dielectric material on a package dielectric material, and then forming a conductive material on the CVD dielectric material.

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a CVD dielectric material on a package dielectric material, and then forming a conductive material on the CVD dielectric material.

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for formation of a dielectric with a smooth surface. In one embodiment, a method includes providing a dielectric with first and second surfaces, a conductive feature formed on the first surface, and a laminate applied to the second surface, curing the second surface while the laminate remains applied, and removing the laminate. Other embodiments may be described and/or claimed.

Abstract: Bumpless build-up layer (BBUL) semiconductor packages with ultra-thin dielectric layers are described. For example, an apparatus includes a semiconductor die including an integrated circuit having a plurality of external conductive bumps. A semiconductor package houses the semiconductor die. The semiconductor package includes a dielectric layer disposed above the plurality of external conductive bumps. A conductive via is disposed in the dielectric layer and coupled to one of the plurality of conductive bumps. A conductive line is disposed on the dielectric layer and coupled to the conductive via.

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a CVD dielectric material on a package dielectric material, and then forming a conductive material on the CVD dielectric material.

Abstract: Ferroelectric polymer memory modules are described. In an example, a module has a first set of layers including a first ILD layer defining trenches therein, a first electrode layer disposed in the trenches of the first ILD layer, a first conductive polymer layer disposed on the first electrode layer and in the trenches of the first ILD layer, and a ferroelectric polymer layer disposed on the first conductive polymer layer, in and extending beyond the trenches of the first ILD layer. The module also has a second set of layers disposed on the first set of layers to define memory cells therewith. The second set of layers includes a second ILD layer defining trenches therein, a second conductive polymer layer disposed in the trenches of the second ILD layer, and a second electrode layer disposed on the second conductive polymer layer.

Abstract: A method of fabricating a ferroelectric memory module with conducting polymer electrodes, and a ferroelectric memory module fabricated according to the method. The ferroelectric polymer memory module includes a first set of layers including: an ILD layer defining trenches therein; a first electrode layer disposed in the trenches; a first conductive polymer layer disposed on the first electrode layer; and a ferroelectric polymer layer disposed on the first conductive polymer layer. The module further includes a second set of layers including: an ILD layer defining trenches therein; a second conductive polymer layer disposed in the trenches of the ILD layer of the second set of layers; and a second electrode layer disposed on the second conductive polymer layer. The first conductive polymer layer and the second conductive polymer layer cover the electrode layers to provide a reaction and/or diffusion barrier between the electrode layers and the ferroelectric polymer layer.

Abstract: A ferroelectric polymer memory module includes a first set of layers including: a first ILD layer defining trenches therein; a first electrode layer disposed in the trenches of the first ILD layer; a first conductive polymer layer disposed on the first electrode layer and in the trenches of the first ILD layer; and a ferroelectric polymer layer disposed on the first conductive polymer layer and in the trenches of the first ILD layer; and a second set of layers disposed on the first set of layers to define memory cells therewith, the second set of layers including: a second ILD layer defining trenches therein; a second conductive polymer layer disposed in the trenches of the second ILD layer; and a second electrode layer disposed on the second conductive polymer layer.

Abstract: According to one aspect of the invention, a method of constructing a memory array is provided. An insulating layer is formed on a semiconductor wafer. A first metal stack is then formed on the insulating layer and etched to form first metal lines. A polymeric layer is formed over the first metal lines and the insulating layer. A puddle of smoothing solvent is then allowed to stand on the wafer. The smoothing solvent is then removed. After the smoothing solvent is removed, the polymeric layer has a reduced surface roughness. A second metal stack is then formed on the polymeric layer and etched to form second metal lines.

Abstract: An embodiment mitigates one or more of the limiting factors of fabricating polymer ferroelectric memory devices. For example, an embodiment reduces the degradation of the ferroelectric polymer due to the polymer's reaction with, and migration or diffusion of, adjacent metal electrode material. Further, the ferroelectric polymer is exposed to fewer potentially high temperature or high energy processes that may damage the polymer. An embodiment further incorporates an immobilized catalyst to improve the adhesion between adjacent layers, and particularly between the electrolessly plated electrodes and the ferroelectric polymer.

Abstract: A technique includes forming overlaying magnetic metal layers over a semiconductor substrate. The technique includes forming at least one resistance layer between the magnetic metal layers.

Abstract: In accordance with some embodiments, a ferroelectric polymer memory may be formed of a plurality of stacked layers. Each layer may be separated from the ensuing layer by a polyimide layer. The polyimide layer may provide reduced layer-to-layer coupling, and may improve planarization after the lower layer fabrication.