Abstract: An embodiment mitigates one or more of the limiting factors of fabricating polymer ferroelectric memory devices. For example, an embodiment reduces the degradation of the ferroelectric polymer due to the polymer's reaction with, and migration or diffusion of, adjacent metal electrode material. Further, the ferroelectric polymer is exposed to fewer potentially high temperature or high energy processes that may damage the polymer. An embodiment further incorporates an immobilized catalyst to improve the adhesion between adjacent layers, and particularly between the electrolessly plated electrodes and the ferroelectric polymer.

Abstract: A ferroelectric memory device and a method of formation are disclosed. In one particular embodiment, a ferroelectric memory device comprises a first electrode layer formed on a substrate, a ferroelectric polymer layer formed on substantial portion of a first electrode layer, a thin layer of conductive ferroelectric polymer formed on a substantial portion of the ferroelectric polymer layer, where the ferroelectric polymer may be made conductive by doping with conductive nano-particles, and a second electrode layer formed on at least a portion of the carbon doped ferroelectric polymer layer.

Abstract: According to one aspect of the invention, a method of constructing a memory array is provided. An insulating layer is formed on a semiconductor wafer. A first metal stack is then formed on the insulating layer and etched to form first metal lines. A polymeric layer is formed over the first metal lines and the insulating layer. A puddle of smoothing solvent is then allowed to stand on the wafer. The smoothing solvent is then removed. After the smoothing solvent is removed, the polymeric layer has a reduced surface roughness. A second metal stack is then formed on the polymeric layer and etched to form second metal lines.

Abstract: According to one aspect of the invention, a method of constructing a memory array is provided. An insulating layer is formed on a semiconductor wafer. A first metal stack is then formed on the insulating layer and etched to form first metal lines. A polymeric layer is formed over the first metal lines and the insulating layer. A puddle of smoothing solvent is then allowed to stand on the wafer. The smoothing solvent is then removed. After the smoothing solvent is removed, the polymeric layer has a reduced surface roughness. A second metal stack is then formed on the polymeric layer and etched to form second metal lines.

Abstract: Methods for improving the net remnant polarization of a polymer memory cell are disclosed. In one embodiment, the polymer material is heated above the Curie temperature of the polymer material, and the domains of the polymer material are aligned with an externally applied electric field.

Abstract: On-die inductively coupled wires and a method of making on-die inductively coupled wires are described. The on-die inductively coupled wires include a first wire to carry a first current, a surface area bounded by a second wire, and, a layer to couple magnetic flux induced by said the first current through the surface area. The layer comprises regions of dielectric material and regions of soft magnetic material.

Abstract: A technique includes forming overlaying magnetic metal layers over a semiconductor substrate. The technique includes forming at least one resistance layer between the magnetic metal layers.

Abstract: A ferroelectric memory device and a method of formation are disclosed. In one particular embodiment, a ferroelectric memory device comprises a first electrode layer formed on a substrate, a ferroelectric polymer layer formed on substantial portion of a first electrode layer, a thin layer of conductive ferroelectric polymer formed on a substantial portion of the ferroelectric polymer layer, where the ferroelectric polymer may be made conductive by doping with conductive nano-particles, and a second electrode layer formed on at least a portion of the carbon doped ferroelectric polymer layer.

Abstract: Embodiments of the invention provide a method for producing ferroelectric polymer devices (FPMDs) employing conditions that avoid or reduce detrimental impact on the ferroelectric polymer film. For one embodiment, a damascene patterning metallization technique is used. For one embodiment a first metal layer is deposited on a substrate to form the bottom electrode for the FPMD. The first metal layer is capped with a selectively deposited diffusion barrier. A layer of ferroelectric polymer film is then deposited on the first conductive layer. The ferroelectric polymer film is planarized. A second metal layer is deposited on the ferroelectric polymer film layer to form the top electrode of the FPMD. The second metal layer is deposited such that the ferroelectric polymer film is not substantially degraded. For various alternative embodiments the various component processes may be accomplished at temperatures far below those employed in a conventional damascene patterning metallization process.

Abstract: Methods of fabricating an interconnect, which fundamentally comprises etching back on an overhang section formed over a portion of an opening formed in a dielectric layer, said etching back is selected from one of an electropolishing process and chemical etching process, and said etching back removes the overhang section at a controlled etch rate of about 10 ?/sec to 70 ?/sec; and depositing a conductive material into the opening so as to fill the opening and form an interconnect.

Abstract: According to one aspect of the invention, a method of constructing a memory array is provided. An insulating layer is formed on a semiconductor wafer. A first metal stack is then formed on the insulating layer and etched to form first metal lines. A polymeric layer is formed over the first metal lines and the insulating layer. A puddle of smoothing solvent is then allowed to stand on the wafer. The smoothing solvent is then removed. After the smoothing solvent is removed, the polymeric layer has a reduced surface roughness. A second metal stack is then formed on the polymeric layer and etched to form second metal lines.

Abstract: According to one aspect of the invention, a memory array and a method of constructing a memory array are provided. An insulating layer is formed on a semiconductor substrate. A first metal stack is then formed on the insulating layer. The first metal stack is etched to form first metal lines. A polymeric layer is formed over the first metal lines and the insulating layer. The polymeric layer has a surface with a plurality of roughness formations. A second metal stack is formed on the polymeric layer with an interface layer, which is thicker than the heights of the roughness formations. Then the second metal stack is etched to form second metal lines. Memory cells are formed wherever a second metal line extends over a first metal line.

Abstract: The present invention describes a structure having a multilayer stack of thin films, the thin films being a low-dielectric constant material, the thin films having pores, and a method of forming such a structure.

Abstract: A controlled collapse chip connection (C4) comprises a copper metal C4 bump formed on an integrated circuit substrate, where the C4 bump includes a metal barrier cap to prevent electromigration of the copper metal. The barrier cap is formed from nickel or cobalt and it can either be formed on a top surface of the C4 bump or it can encapsulate the C4 bump. A method of forming the C4 bump with the barrier cap comprises providing an integrated circuit substrate, depositing a photoresist layer on a top surface of the integrated circuit substrate, exposing and developing the photoresist layer to form an opening, depositing copper metal into the opening to form a C4 bump, plating a metal barrier layer onto a surface of the C4 bump, and stripping the photoresist layer.

Abstract: A series of address lines extend in a first direction through at least two layers of memory material spaced apart in the first direction. The memory material may be a ferroelectric polymer in one embodiment. The arrangement of lines and layers may increase the density of a memory in one embodiment.

Abstract: According to one aspect of the invention, a memory array and a method of constructing a memory array are provided. An insulating layer is formed on a semiconductor substrate. A first metal stack is then formed on the insulating layer. The first metal stack is etched to form first metal lines. A polymeric layer is formed over the first metal lines and the insulating layer. The polymeric layer has a surface with a plurality of roughness formations. A second metal stack is formed on the polymeric layer with an interface layer, which is thicker than the heights of the roughness formations. Then the second metal stack is etched to form second metal lines. Memory cells are formed wherever a second metal line extends over a first metal line.

Abstract: According to one aspect of the invention, a method of constructing a memory array is provided. An insulating layer is formed on a semiconductor wafer. A first metal stack is then formed on the insulating layer and etched to form first metal lines. A polymeric layer is formed over the first metal lines and the insulating layer. A puddle of smoothing solvent is then allowed to stand on the wafer. The smoothing solvent is then removed. After the smoothing solvent is removed, the polymeric layer has a reduced surface roughness. A second metal stack is then formed on the polymeric layer and etched to form second metal lines.

Abstract: A memory circuit is provided with a spacer formed on a support surface and positioned adjacent to a first electrode surface of a first electrode. The memory circuit further includes a ferroelectric layer formed on the first electrode and the spacer.

Abstract: Polymer electronics devices having reliable electrical contacts and methods of their fabrication are described. A surface of a conductive layer is modified, and a layer of polymer is formed on a modified surface of the conductive layer to create an electrical contact between the conductive layer and the layer of polymer. The electrical contact is created without adding an adhesion promoter. Modifying the surface of the conductive layer increases surface area of conductive layer and therefore improves polymer to conductive layer adhesion while preserving an original chemistry of the surface of the conductive layer. The modified surface of the conductive layer may be formed by mechanical roughening, chemical roughening, or both. The conductive layer forming the electrical contact to the polymer includes a noble metal. The polymer may be spin coated over the modified surface of the conductive layer.

Abstract: A ferroelectric polymer memory device and a method of providing an electrode layer of the device. The device comprises: a substrate; a plurality of electrode layers including a first electrode layer disposed on the substrate and a second electrode layer extending at an angle with respect to the first electrode layer in a longitudinal direction thereof; a ferroelectric layer disposed between the first electrode layer and the second electrode layer to form memory cells; a ILD layer disposed on the second electrode layer; wherein at least one of the plurality of electrode layers exhibits a pyramidal profile in a widthwise cross-section thereof.