Abstract: A method for improving thickness uniformity and throughput of a carbon doped oxide deposition process is described. That method comprises removing pre-deposition steps in a deposition phase. Moreover, helium plasma is added to a pre-clean phase to eliminate the production of dummy wafers.

Abstract: An embodiment mitigates one or more of the limiting factors of fabricating polymer ferroelectric memory devices. For example, an embodiment reduces the degradation of the ferroelectric polymer due to the polymer's reaction with, and migration or diffusion of, adjacent metal electrode material. Further, the ferroelectric polymer is exposed to fewer potentially high temperature or high energy processes that may damage the polymer. An embodiment further incorporates an immobilized catalyst to improve the adhesion between adjacent layers, and particularly between the electrolessly plated electrodes and the ferroelectric polymer.

Abstract: A process for forming an interlayer dielectric layer is disclosed. The method comprises first forming a carbon-doped oxide (CDO) layer with a first concentration of carbon dopants therein. Next, the CDO layer is further formed with a second concentration of carbon dopants therein, wherein the first concentration is different than the second concentration.

Abstract: Embodiments of the invention provide a method for producing ferroelectric polymer devices (FPMDs) employing conditions that avoid or reduce detrimental impact on the ferroelectric polymer film. For one embodiment, a damascene patterning metallization technique is used. For one embodiment a first metal layer is deposited on a substrate to form the bottom electrode for the FPMD. The first metal layer is capped with a selectively deposited diffusion barrier. A layer of ferroelectric polymer film is then deposited on the first conductive layer. The ferroelectric polymer film is planarized. A second metal layer is deposited on the ferroelectric polymer film layer to form the top electrode of the FPMD. The second metal layer is deposited such that the ferroelectric polymer film is not substantially degraded. For various alternative embodiments the various component processes may be accomplished at temperatures far below those employed in a conventional damascene patterning metallization process.

Abstract: A low temperature plasma ashing process for use with substrates comprising a ferroelectric material. The process generally includes plasma ashing the photoresist and residues at a temperature of about room temperature to about 140° C., wherein the plasma is generated from a gas mixture consisting essentially of hydrogen and an inert gas, and wherein the ferroelectric material is exposed to the plasma.

Abstract: Embodiments of the invention provide a method for producing ferroelectric polymer devices (FPMDs) employing conditions that avoid or reduce detrimental impact on the ferroelectric polymer film. For one embodiment, a damascene patterning metallization technique is used. For one embodiment a first metal layer is deposited on a substrate to form the bottom electrode for the FPMD. The first metal layer is capped with a selectively deposited diffusion barrier. A layer of ferroelectric polymer film is then deposited on the first conductive layer. The ferroelectric polymer film is planarized. A second metal layer is deposited on the ferroelectric polymer film layer to form the top electrode of the FPMD. The second metal layer is deposited such that the ferroelectric polymer film is not substantially degraded. For various alternative embodiments the various component processes may be accomplished at temperatures far below those employed in a conventional damascene patterning metallization process.

Abstract: An electrode layer for a polymer memory may be implanted to increase the number of defects in the material. As a result, that same material may be utilized for the upper and lower electrodes. In particular, defects may be introduced into a TiOx layer within the electrode to match the work functions of the upper and lower electrodes.

Abstract: The present invention describes a structure having a multilayer stack of thin films, the thin films being a low-dielectric constant material, the thin films having pores, and a method of forming such a structure.

Abstract: Methods of depositing various metal layers adjacent to a ferroelectric polymer layer are disclosed. In one embodiment, a collimator may be used during a sputtering process to filter out charged particles from the material that may be deposited as a metal layer. In various embodiments, a metal layer may contain at least one of an intermetallic layer, an amorphous intermetallic layer, and an amorphized intermetallic layer.

Abstract: A ferroelectric memory device and a method of formation are disclosed. In one particular embodiment, a ferroelectric memory device comprises a first electrode layer formed on a substrate, a ferroelectric polymer layer formed on substantial portion of a first electrode layer, a thin layer of conductive ferroelectric polymer formed on a substantial portion of the ferroelectric polymer layer, where the ferroelectric polymer may be made conductive by doping with conductive nano-particles, and a second electrode layer formed on at least a portion of the carbon doped ferroelectric polymer layer.

Abstract: A method of fabricating a ferroelectric memory module with conducting polymer electrodes, and a ferroelectric memory module fabricated according to the method. The ferroelectric polymer memory module includes a first set of layers including: an ILD layer defining trenches therein; a first electrode layer disposed in the trenches; a first conductive polymer layer disposed on the first electrode layer; and a ferroelectric polymer layer disposed on the first conductive polymer layer. The module further includes a second set of layers including: an ILD layer defining trenches therein; a second conductive polymer layer disposed in the trenches of the ILD layer of the second set of layers; and a second electrode layer disposed on the second conductive polymer layer. The first conductive polymer layer and the second conductive polymer layer cover the electrode layers to provide a reaction and/or diffusion barrier between the electrode layers and the ferroelectric polymer layer.

Abstract: In accordance with some embodiments, a ferroelectric polymer memory may be formed of a plurality of stacked layers. Each layer may be separated from the ensuing layer by a polyimide layer. The polyimide layer may provide reduced layer-to-layer coupling, and may improve planarization after the lower layer fabrication.

Abstract: A series of conductive layers separated by interlayer gaps is formed adjacent a substrate layer, the conductive layer and interlayer gap dimensions defining aspect ratios for trenches between the conductive layers. A layer of dielectric material is deposited over the conductive layers using plasma enhanced chemical vapor deposition. Trenches having aspect ratios within specified geometric categories are incompletely filled, leaving interlayer voids which may have desirable dielectric properties.

Abstract: Some embodiments for a method to fill interlayer vias with a suitable metal in a ferroelectric polymer memory die to reduce the step height and improve the thermal and electrical properties of the via. The method uses an electroless plating method to fill the vias, which is compatible with the ferroelectric polymer memory die processing temperature limits. The resulting process produces via fill metal plugs in the ferroelectric memory die, which allows for the deposition of a thin metal layer over the vias, while at the same time improving the electrical and thermal properties of the vias. Other embodiments are described and claimed herein.

Abstract: An embodiment of the invention is a method of removing photoresist. More specifically, an embodiment is a method of removing photoresist utilized to pattern the top electrode metal layer in a polymer memory device substantially without damaging the underlying polymer or top electrode metal by utilizing a high pressure photoresist solvent spray.

Abstract: Methods of depositing various metal layers adjacent to a ferroelectric polymer layer are disclosed. In one embodiment, a collimator may be used during a sputtering process to filter out charged particles from the material that may be deposited as a metal layer. In various embodiments, a metal layer may contain at least one of an intermetallic layer, an amorphous intermetallic layer, and an amorphized intermetallic layer.

Abstract: A technique to promote the adhesion and uniform distribution of a spin coated film upon a ferroelectric material. At least one embodiment of the invention uses a ferroelectric material, such as PVDF/TrFE, to promote the adhesion of a spin-coated film onto a wafer.

Abstract: A ferroelectric memory device and a method of formation are disclosed. In one particular embodiment, a ferroelectric memory device comprises a first electrode layer formed on a substrate, a ferroelectric polymer layer formed on substantial portion of a first electrode layer, a thin layer of conductive ferroelectric polymer formed on a substantial portion of the ferroelectric polymer layer, where the ferroelectric polymer may be made conductive by doping with conductive nano-particles, and a second electrode layer formed on at least a portion of the carbon doped ferroelectric polymer layer.

Abstract: The present invention describes a method for creating a differential polish rate across a semiconductor wafer. The profile or topography of the semiconductor wafer is determined by locating the high points and low points of the wafer profile. The groove pattern of a polish pad is then adjusted to optimize the polish rate with respect to the particular wafer profile. By increasing the groove depth, width, and/or density of the groove pattern of the polish pad the polish rate may be increased in the areas that correspond to the high points of the wafer profile. By decreasing the groove depth, width, and/or density of the groove pattern of the polish pad the polish rate may be decreased in the areas that correspond to the low points of the wafer profile. A combination of these effects may be desirable in order to stabilize the polish rate across the wafer surface in order to improve the planarization of the polishing process.

Abstract: A ferroelectric memory device and a method of formation are disclosed. In one particular embodiment, a ferroelectric memory device comprises a first electrode layer formed on a substrate, a ferroelectric polymer layer formed on substantial portion of a first electrode layer, a thin layer of conductive ferroelectric polymer formed on a substantial portion of the ferroelectric polymer layer, where the ferroelectric polymer may be made conductive by doping with conductive nano-particles, and a second electrode layer formed on at least a portion of the carbon doped ferroelectric polymer layer.