Abstract: Disclosed is a method of fabricating an integrated circuit comprising patterning a dielectric layer to form a hole having a sidewall and a bottom. The hole can expose an underlying material of an electrically conducting material. The method also includes exposing the sidewall and the exposed underlying material to a plasma etch, depositing a barrier layer on the bottom and the sidewall of the hole after the plasma etch clean, forming a counter-sunk cone in the underlying material by etching through the barrier layer at the bottom of the hole into the conducting metal underneath, flash depositing a thin layer of the barrier material into the hole, and finally depositing a metal seed layer in the hole covering the sidewalls and the bottom of the hole including the cone at the bottom. The hole is finally filled by depositing a metal layer in the hole.

Abstract: Provided herein are improved methods of collecting and recovering placental cells from a mammalian placenta, comprising, e.g., perfusing a mammalian placenta in a closed system such as a sterile bag and folding the placenta at least once during perfusion. Such folding, and perfusion, can be performed mechanically.

Abstract: A weep hole screen and method for installing the same in the exterior wall of a masonry building in order to prevent small animals such as insects and rodents from entering the building through the weep hole. A weep hole screen in accordance with the present invention preferably comprises a rectangular mesh screen with an angle bracket attached to each end. The weep hole screen is sized such that the angle brackets sandwich the bricks that form the weep hole, preferably on the interior faces of the bricks. The interfaces between the weep hole screen and the bricks are preferably sealed with mortar or another suitable sealant. The weep hole screen may be installed easily during original construction of the wall without the need for any mechanical fasteners.

Abstract: A method of preparing a thin film on a substrate is described. The method comprises forming an ultra-thin hermetic film over a portion of a substrate using a gas cluster ion beam (GCIB), wherein the ultra-thin hermetic film has a thickness less than approximately 5 nm. The method further comprises providing a substrate in a reduced-pressure environment, and generating a GCIB in the reduced-pressure environment from a pressurized gas mixture. A beam acceleration potential and a beam dose are selected to achieve a thickness of the thin film less than about 5 nanometers (nm). The GCIB is accelerated according to the beam acceleration potential, and the accelerated GCIB is irradiated onto at least a portion of the substrate according to the beam dose. By doing so, the thin film is formed on the at least a portion of the substrate to achieve the thickness desired.

Abstract: A method of forming a thin film on a substrate is described. The method comprises depositing a first material layer on a substrate using a first gas cluster ion beam (GCIB), the first material layer comprising a first atomic constituent, and growing a second material layer from at least a surface portion of the first material layer by introducing a second atomic constituent using a second GCIB, the second material layer comprising a reaction product of the first and second atomic constituents.

Abstract: A method of forming shallow trench isolation on a substrate using a gas cluster ion beam (GCIB) is described. The method comprises generating a GCIB, and irradiating the substrate with the GCIB to form a shallow trench isolation structure by depositing a dielectric layer in at least one region on the substrate.

Abstract: An on-chip decoupling capacitor (106) and method of fabrication. The decoupling capacitor (106) is integrated at the top metal interconnect level (104) and includes surface protection cladding (109) for the copper metal (104b) of the top metal interconnect.

Abstract: An on-chip decoupling capacitor (106) and method of fabrication. The decoupling capacitor (106) is integrated at the top metal interconnect level (104) and includes surface protection cladding (109) for the copper metal (104b) of the top metal interconnect.

Abstract: A weep hole screen and method for installing the same in the exterior wall of a masonry building in order to prevent small animals such as insects and rodents from entering the building through the weep hole. A weep hole screen in accordance with the present invention preferably comprises a rectangular mesh screen with an angle bracket attached to each end. The weep hole screen is sized such that the angle brackets sandwich the bricks that form the weep hole, preferably on the interior faces of the bricks. The interfaces between the weep hole screen and the bricks are preferably sealed with mortar or-another suitable sealant. The weep hole screen may be installed easily during original construction of the wall without the need for any mechanical fasteners.

Abstract: A method of manufacturing an integrated circuit comprising fabricating a dual damascene interconnect. Fabricating the interconnect including forming a via opening in a surface of an inter-layer dielectric (ILD) located over a semiconductor substrate. Fabricating the interconnect also includes depositing a sacrificial fill material over the surface and in the via opening. Fabricating the interconnect further includes removing the sacrificial fill material from the surface, depositing a poison-blocking-layer over the surface and forming a trench pattern in a photoresist layer formed over the poison-blocking-layer. The poison-blocking-layer is configured to prevent poisons from entering the photoresist layer.

Abstract: An on-chip decoupling capacitor (106) and method of fabrication. The decoupling capacitor (104) is integrated at the top metal interconnect level (104) and may be implemented with only one additional masking layer. The decoupling capacitor (106) is formed on a copper interconnect line (104a). An aluminum cap layer (118) provides electrical connection to the top electrode (112) of the decoupling capacitor (106).

Abstract: An on-chip decoupling capacitor (106) and method of fabrication. The decoupling capacitor (104) is integrated at the top metal interconnect level (104) and may be implemented with only one additional masking layer. The decoupling capacitor (106) is formed on a copper interconnect line (104a). An aluminum cap layer (118) provides electrical connection to the top electrode (112) of the decoupling capacitor (106).

Abstract: An on-chip decoupling capacitor (106) and method of fabrication. The decoupling capacitor (106) is integrated at the top metal interconnect level (104) and includes surface protection layer (109) for the copper metal (104b) of the top metal interconnect.

Abstract: Disclosed is a method of fabricating an integrated circuit comprising patterning a dielectric layer to form a hole having a sidewall and a bottom. The hole can expose an underlying material of an electrically conducting material. The method also includes exposing the sidewall and the exposed underlying material to a plasma etch, depositing a barrier layer on the bottom and the sidewall of the hole after the plasma etch clean, forming a counter-sunk cone in the underlying material by etching through the barrier layer at the bottom of the hole into the conducting metal underneath, flash depositing a thin layer of the barrier material into the hole, and finally depositing a metal seed layer in the hole covering the sidewalls and the bottom of the hole including the cone at the bottom. The hole is finally filled by depositing a metal layer in the hole.

Abstract: A capacitive structure (10). The capacitive structure comprises a semiconductor base region (30) having an upper surface, a well (12) formed within the semiconductor base region and adjacent the upper surface, a first dielectric layer (38) adjacent at least a portion of the upper surface, and a polysilicon layer (16) adjacent the first dielectric layer. The well, the first dielectric layer, and the first polysilicon layer form a first capacitor and are aligned along a planar dimension. The capacitive structure further comprises a first conductive layer (201) positioned with at least a portion overlying at least a portion of the polysilicon layer, a second dielectric layer (202) adjacent the first conductive layer, and a second conductive layer (203) adjacent the second dielectric layer. The first conductive layer, the second dielectric layer, and the second conductive layer form a second capacitor and are aligned along the planar dimension.

Abstract: An embodiment of the invention is a capacitor comprising a bottom electrode 70 coupled to a first interconnect 30a of the top metal level 10, a capacitor dielectric 90, sidewalls 105, and a top electrode 110 coupled to a second interconnect 30b of the top metal level 10. Another embodiment of the invention is a method of manufacturing a capacitor using a first mask 140 to form a material stack that includes a bottom electrode 70 coupled to a first interconnect 30a of the top metal level 10, a capacitor dielectric 90, and a partial top electrode 100. The method further includes using a second mask 150 to form a complete top electrode coupled to a second interconnect 30b of the top metal level 10.

Abstract: An embodiment of the invention is a capacitor comprising a bottom electrode 70 coupled to a first interconnect 30a of the top metal level 10, a capacitor dielectric 90, sidewalls 105, and a top electrode 110 coupled to a second interconnect 30b of the top metal level 10. Another embodiment of the invention is a method of manufacturing a capacitor using a first mask 140 to form a material stack that includes a bottom electrodes 70 coupled to a first interconnect 30a of the top metal level 10, a capacitor dielectric 90, and a partial top electrode 100. The method further includes using a second mask 150 to form a complete top electrode coupled to a second interconnect 30b of the top metal level 10.

Abstract: An on-chip decoupling capacitor (106) and method of fabrication. The decoupling capacitor (104) is integrated at the top metal interconnect level (104) and may be implemented with only one additional masking layer. The decoupling capacitor (106) is formed on a copper interconnect line (104a). An aluminum cap layer (118) provides electrical connection to the top electrode (112) of the decoupling capacitor (106).

Abstract: An on-chip decoupling capacitor (106) and method of fabrication. The decoupling capacitor (106) is integrated at the top metal interconnect level (104) and includes surface protection layer (109) for the copper metal (104b) of the top metal interconnect.