Abstract: An on-chip decoupling capacitor (106) and method of fabrication. The decoupling capacitor (106) is integrated at the top metal interconnect level (104) and includes surface protection cladding (109) for the copper metal (104b) of the top metal interconnect.

Abstract: A capacitive structure (10). The capacitive structure comprises a semiconductor base region (30) having an upper surface, a well (12) formed within the semiconductor base region and adjacent the upper surface, a first dielectric layer (38) adjacent at least a portion of the upper surface, and a polysilicon layer (16) adjacent the first dielectric layer. The well, the first dielectric layer, and the first polysilicon layer form a first capacitor and are aligned along a planar dimension. The capacitive structure further comprises a first conductive layer (201) positioned with at least a portion overlying at least a portion of the polysilicon layer, a second dielectric layer (202) adjacent the first conductive layer, and a second conductive layer (203) adjacent the second dielectric layer. The first conductive layer, the second dielectric layer, and the second conductive layer form a second capacitor and are aligned along the planar dimension.

Abstract: An embodiment of the invention is a capacitor comprising a bottom electrode 70 coupled to a first interconnect 30a of the top metal level 10, a capacitor dielectric 90, sidewalls 105, and a top electrode 110 coupled to a second interconnect 30b of the top metal level 10. Another embodiment of the invention is a method of manufacturing a capacitor using a first mask 140 to form a material stack that includes a bottom electrode 70 coupled to a first interconnect 30a of the top metal level 10, a capacitor dielectric 90, and a partial top electrode 100. The method further includes using a second mask 150 to form a complete top electrode coupled to a second interconnect 30b of the top metal level 10.

Abstract: An embodiment of the invention is a capacitor comprising a bottom electrode 70 coupled to a first interconnect 30a of the top metal level 10, a capacitor dielectric 90, sidewalls 105, and a top electrode 110 coupled to a second interconnect 30b of the top metal level 10. Another embodiment of the invention is a method of manufacturing a capacitor using a first mask 140 to form a material stack that includes a bottom electrode 70 coupled to a first interconnect 30a of the top metal level 10, a capacitor dielectric 90, and a partial top electrode 100. The method further includes using a second mask 150 to form a complete top electrode coupled to a second interconnect 30b of the top metal level 10.

Abstract: A data error detection method for a bit, byte or word oriented network wherein a protected data unit 46 and an associated data check unit 50 are addressed to a particular field device located on the network, 10 or 26. The data check unit 50 is derived in a particular manner either solely from the protected data unit 46 or from the protected data unit 46 and particular binary codes representing attributes of the network 10 or 26 and the field device sending the protected data unit 46. The particular configuration of the checking data unit 50 is such that the receiving field device or the host 22 can perform a bit-by-bit comparison of either the received protected data unit 46 or data check unit 50 with a protected data unit 46 or data check unit 50 derived in the particular manner by the receiving host 22 or field device 14 or 18.

Abstract: A method is provided for forming a local interconnect (24) at a face of semiconductor workpiece (10). A layer of conductive material (24) is formed across the workpiece face, followed by the formation of a layer (28) of photoresist adjacent the layer of conductive material (24). The layer of photoresist (28) is patterned to define selected areas of the layer of conductive material (24) to be removed. A dry etch is performed, using a plasma established in a gaseous mixture of carbon tetrachloride, carbon tetrafluoride, and helium, to remove the selected areas of the conductive material and conductive filaments (26) formed at the face of workpiece (10).