Abstract: A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system.Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets.CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.

Abstract: A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system.Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets.CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.

Abstract: A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. The CPUs are structured to operate in one of two modes: a simplex mode in which the two CPUs operate independently of each other, and a duplex mode in which the CPUs operate in lock-step synchronism to execute each instruction of identical instruction streams at substantially the same time. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system.

Abstract: Compound of the formula C.sub.6 F.sub.12 --CH.sub.2 CH.sub.2 --SO.sub.3 M wherein M is a cation having a valence of 1 is used as a dispersing agent in the aqueous dispersion polymerization of tetrafluoroethylene.

Abstract: A processing system includes a number of communicatively interconnected system elements structured to send and receive data in the form of message packets. Message packets sent to a destination with expectation of response are timed, and if no response is received within an allotted time, a barrier transaction message packet is sent to the destination. The destination is required to provide a barrier transaction response to the barrier transaction packet only after it has responded to, or discarded, all prior received message packets requiring response by the destination. When the source of the barrier transaction message packet receives the barrier transaction response it can be assured that the communication path to the destination is in order, and no prior (late) responses will be forthcoming.

Abstract: A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system.Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets, and stored at an interrupt queue in memory. Storage of the interrupt data will initiate an internal interrupt to notify the receiving CPU. The receiving CPU can then access the interrupt queue, examine the interrupt data, and determine what action to take.

Abstract: A storage system comprising a plurality of shelf units adapted to be stacked vertically upon one another. Each of the shelf units includes a relatively rigid, horizontally disposed shelf member and a liner member fabricated of an inexpensive, yet relatively strong and durable material, such as corrugated paperboard, cardboard or the like. The vertically stacked shelf units are adapted to be mounted upon either a fixed or a rolling base, and in the case of a rolling base, said base may be operatively associated with a track system whereby vertically stacked assemblies of the storage shelf units may be moved along the track system to provide a highly compact storage system incorporating only a single aisleway for multiple storage units.

Abstract: This disclosure relates to the refeeding of one or more electrodes of an electrical discharge machining apparatus after the electrodes have been used and unevenly worn. The electrodes are mounted within a cartridge which includes an element which offers frictional resistance to the movement of the electrodes relative to the cartridge so that when the cartridge is advanced to engage the electrodes with a workpiece the electrodes are automatically recessed within the cartridge until the tips of all electrodes are aligned. A clamp is provided for then securely clamping the electrodes against further movement relative to the cartridge.

Abstract: This invention discloses a cartridge for containing electrodes which are fed to the nose guide of an electrical discharge machining apparatus. The cartridge has a carriage which contains the electrodes and moves with respect to the nose guide. An electrode clamp is provided to lock the electrodes in position in the cartridge together with means offering frictional resistance to sliding movement of the electrodes upon release of the clamp.

Abstract: A storage system comprising a plurality of generally aligned storage units, each of the units including at least two storage sections arranged in side-by-side relation, the units being supported for movement along a predetermined substantially linear path by means of a plurality of generally parallel arranged tracks, with one pair of tracks being associated with each of the storage sections, the tracks being relatively flexible so as to be adapted to be laid directly upon and contiguously conform to a relatively irregular support surface; and a base structure on each of the storage sections and provided with pairs of spaced rollers adapted to ride upon and traverse mating pairs of tracks, the storage sections of each of the units being connected together but acting individually with their mating tracks and independently of the adjacent tracks as the storage units traverse the tracks along the aforesaid path.

Abstract: In a prover loop used to calibrate positive displacement meters, such as those used on a LACT-unit (Lease Automatic Custody Transfer) in the petroleum industry, a control system is provided for operating the prover loop valve. This control system is designed to operate so that each prover loop test is conducted under identical conditions. The system design permits easy conversion from the conventional hydraulic systems.