Abstract: A level shifter circuit includes a first current mirror coupled between a power terminal and a ground terminal, a second current mirror coupled between the power terminal and the ground terminal, and a level shifter. The level shifter includes a first transistor coupled to the first current mirror and a second transistor coupled to the second current mirror. The first current mirror and the second current mirror control a state of the first transistor and the second transistor.

Abstract: A system and method for characterizing a memory instance. Characterizing a memory instance includes obtaining a memory instance comprising a plurality of leaf cells. Each of the plurality of leaf cells comprises components. First channel connected components from the components within each of the plurality of leaf cells are determined, and a first super leaf cell is generated by combining a first two or more leaf cells of the plurality of leaf cells based on the first channel connected components. Further, an updated memory instance is generated based on the first super leaf cell, and a timing model is determined for the updated memory instance.

Abstract: A memory device includes clock signal generation circuitry, and first integrated level shifter and latch circuitry. The clock signal generation circuitry receives a first clock signal and an isolation signal, and generates a second clock signal based on the first clock signal and the isolation signal. The isolation signal corresponds to a power state of a power supply associated with the first clock signal. The first integrated level shifter and latch circuitry receives an input signal in a first power supply domain, and latches a value the input signal based on the second clock signal. Further, the first integrated level shifter and latch circuitry outputs, based on the latched value, an output signal in a second power supply domain different than the first power supply domain.

Abstract: A method for transient analysis of a memory module circuit, the method including: determining port to port resistances between terminals of internal circuits of a plurality of leaf cells of a netlist representing the memory module circuit; generating a plurality of equivalent networks corresponding to the internal circuits of the leaf cells, the equivalent networks being connected to each other; promoting the equivalent networks of the leaf cells to a hierarchical level above the leaf cells in the netlist representing the memory module circuit; shorting one or more terminals of each of the leaf cells to a central node of a corresponding one of the equivalent networks; and performing the transient analysis of the leaf cells of the netlist representing the memory module circuit.

Abstract: A system and method for generating a netlist of a memory device includes receiving a logical netlist file including memory instances and placement information for the memory device. Each memory instance includes leaf cells. Further, a location of a first leaf cell and a location of a second leaf cell of the leaf cells of a first memory instance is determined based on the placement information. A first net segment between the first leaf cell and the second leaf cell is generated based on the location and parasitic elements of the first leaf cell and the location and parasitic elements of the second leaf cell. A parasitic netlist is generated based on the first net segment and the parasitic elements of the first leaf cell and parasitic elements of the second leaf cell.

Abstract: A system and method for characterizing a memory instance. Characterizing a memory instance includes obtaining a memory instance comprising a plurality of leaf cells. Each of the plurality of leaf cells comprises components. First channel connected components from the components within each of the plurality of leaf cells are determined, and a first super leaf cell is generated by combining a first two or more leaf cells of the plurality of leaf cells based on the first channel connected components. Further, an updated memory instance is generated based on the first super leaf cell, and a timing model is determined for the updated memory instance.

Abstract: A level shifter circuit includes a first current mirror coupled between a power terminal and a ground terminal, a second current mirror coupled between the power terminal and the ground terminal, and a level shifter. The level shifter includes a first transistor coupled to the first current mirror and a second transistor coupled to the second current mirror. The first current mirror and the second current mirror control a state of the first transistor and the second transistor.

Abstract: A memory bypass circuit for a memory device comprises: a word line disable circuit; a read and write activation circuit; an internal clock generator; and a write data input circuit. The word line disable circuit is coupled to a word line of the memory device for disabling a write function to the word line. The read and write activation circuit is coupled to the memory device for reading and writing of input data. The internal clock generator is coupled to the word line disable circuit and the read/write activation circuit. The write data input circuit is coupled to a write driver of the memory device for providing write data.

Abstract: A memory bypass circuit for a memory device comprises: a word line disable circuit; a read and write activation circuit; an internal clock generator; and a write data input circuit. The word line disable circuit is coupled to a word line of the memory device for disabling a write function to the word line. The read and write activation circuit is coupled to the memory device for reading and writing of input data. The internal clock generator is coupled to the word line disable circuit and the read/write activation circuit. The write data input circuit is coupled to a write driver of the memory device for providing write data.

Abstract: An integrated level-shifter and memory clock is disclosed that minimizes delay of voltage level-shifting from an external clock on a first logic supply voltage to an internal clock on a higher array supply voltage that is pulse-width independent of the external clock used to generate the internal clock. The generation of the internal clock on the higher array supply voltages is accomplished in two stages of logic. An array-tracking timing delay circuit mimics access delay to generate a MRST_P to reset the internal clock on the higher array supply voltage.

Abstract: A memory bypass circuit for a memory device comprises: a word line disable circuit; a read and write activation circuit; an internal clock generator; and a write data input circuit. The word line disable circuit is coupled to a word line of the memory device for disabling a write function to the word line. The read and write activation circuit is coupled to the memory device for reading and writing of input data. The internal clock generator is coupled to the word line disable circuit and the read/write activation circuit. The write data input circuit is coupled to a write driver of the memory device for providing write data.

Abstract: A memory bypass circuit for a memory device comprises: a word line disable circuit; a read and write activation circuit; an internal clock generator; and a write data input circuit. The word line disable circuit is coupled to a word line of the memory device for disabling a write function to the word line. The read and write activation circuit is coupled to the memory device for reading and writing of input data. The internal clock generator is coupled to the word line disable circuit and the read/write activation circuit. The write data input circuit is coupled to a write driver of the memory device for providing write data.

Abstract: A sense amplifier for sensing a line of a semiconductor device comprises a p-channel pull-up transistor for charging the line, an inverter, and a pull-up controller. The p-channel pull-up transistor and the inverter are coupled to the line. The inverter inverts a line voltage of the line. The pull-up controller is coupled to the gate of the p-channel pull-up transistor and operates the p-channel pull-up transistor as a function of the inverted line voltage.

Abstract: A content addressable memory (“CAM”) field enabling logic comprises fields and field enable logics. The fields each have local match lines and a corresponding field enable control for enabling the respective field. The field enable logics are serially connected. Each of the fields is coupled to a corresponding one of the field enable logics via the respective local match lines. The corresponding field enable control for each of the fields is coupled to the corresponding one of the field enable logic and to any ones of the field enable logics that come after the corresponding one of the field enable logic along the serially-connected field enable logics.

Abstract: A single ended line sense amplifier having an input coupled to a single ended line having a near end and a far end device comprises a plurality of nFET stacks coupled between the near end of the single ended line and the far end of the single ended line, a single ended line comparator coupled to the near end of the single ended line configured to compare a voltage at the near end of the single ended line to provide a logic state output, and a charge transistor coupled to the single ended line at a point that is between the near end of the single ended line and the far end of the single ended line to shift occurrence of snap back from strong charging of the single ended line.

Abstract: A line sense amplifier comprises: a presearch block, a main search block, and a timing circuit. The presearch block is coupled to a presearch line for sensing the presearch line. The main search block is coupled to a main line for sensing the main line. The timing circuit operates the presearch block and the main search block for charging and sensing of the presearch line and the main line. The timing circuit initiates the main search block to determine a match condition for the main line based on whether a match condition is determined for the presearch line.

Abstract: A single ended line sense amplifier having an input coupled to a single ended line having a near end and a far end device comprises a plurality of nFET stacks coupled between the near end of the single ended line and the far end of the single ended line, a single ended line comparator coupled to the near end of the single ended line configured to compare a voltage at the near end of the single ended line to provide a logic state output, and a charge transistor coupled to the single ended line at a point that is between the near end of the single ended line and the far end of the single ended line to shift occurrence of snap back from strong charging of the single ended line.

Abstract: A line sense amplifier comprises: a presearch block, a main search block, and a timing circuit. The presearch block is coupled to a presearch line for sensing the presearch line. The main search block is coupled to a main line for sensing the main line. The timing circuit operates the presearch block and the main search block for charging and sensing of the presearch line and the main line. The timing circuit initiates the main search block to determine a match condition for the main line based on whether a match condition is determined for the presearch line.

Abstract: A sense amplifier for sensing a line of a semiconductor device comprises a p-channel pull-up transistor for charging the line, an inverter, and a pull-up controller. The p-channel pull-up transistor and the inverter are coupled to the line. The inverter inverts a line voltage of the line. The pull-up controller is coupled to the gate of the p-channel pull-up transistor and operates the p-channel pull-up transistor as a function of the inverted line voltage.

Abstract: A word line driver circuit coupled to a memory circuit word line includes pull-up, pull-up clamp, pull-down and pull-down clamp transistors, each having a source, a drain and a gate. For the pull-up transistor, the source is coupled to a first power supply, and the gate to a pull-up control signal. For the pull-up clamp transistor, the source is coupled to the drain of the pull-up transistor, the drain to the word line, and the gate to a pull-up clamp gate signal. For the pull-down transistor, the source is coupled to a second power supply, and the gate to a pull-down control signal. For the pull-down clamp transistor, the source is coupled to the drain of the pull-down transistor, the drain to the word line, and the gate to a pull-down clamp gate signal. The word line is coupled to one or more DRAM cells. Source to drain voltage magnitudes of the pull-up and pull-down transistors are less than a voltage between the first and second power supplies.