Patents by Inventor Edward Barth
Edward Barth has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110199837Abstract: A word line driver circuit coupled to a memory circuit word line includes pull-up, pull-up clamp, pull-down and pull-down clamp transistors, each having a source, a drain and a gate. For the pull-up transistor, the source is coupled to a first power supply, and the gate to a pull-up control signal. For the pull-up clamp transistor, the source is coupled to the drain of the pull-up transistor, the drain to the word line, and the gate to a pull-up clamp gate signal. For the pull-down transistor, the source is coupled to a second power supply, and the gate to a pull-down control signal. For the pull-down clamp transistor, the source is coupled to the drain of the pull-down transistor, the drain to the word line, and the gate to a pull-down clamp gate signal. The word line is coupled to one or more DRAM cells. Source to drain voltage magnitudes of the pull-up and pull-down transistors are less than a voltage between the first and second power supplies.Type: ApplicationFiled: February 12, 2010Publication date: August 18, 2011Applicant: International Business Machines CorporationInventors: William Robert Reohr, John Edward Barth, JR., Toshiaki Kirihata, Derek H. Leu, Donald W. Plass
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Patent number: 7989865Abstract: A semiconductor structure is disclosed. The semiconductor structure includes an active semiconductor layer, a semiconductor device having a gate disposed on top of the active semiconductor layer, and source and drain regions and a body/channel region disposed within the active semiconductor layer, an insulator layer having a first and second side, the first side being adjacent to the active semiconductor layer, a substrate disposed adjacent to the second side of the insulator layer, a deep trench capacitor disposed under the body/channel region of the semiconductor device. The deep trench capacitor electrically connects with and contacts the body/channel region of the semiconductor device, and is located adjacent to the gate of the semiconductor device. The semiconductor structure increases a critical charge Qcrit, thereby reducing a soft error rate (SER) of the semiconductor device.Type: GrantFiled: August 28, 2008Date of Patent: August 2, 2011Assignee: International Business Machines CorporationInventors: John Edward Barth, Jr., Kerry Bernstein, Ethan Harrison Cannon, Francis Roger White
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Patent number: 7954028Abstract: A design structure for implementing redundancy programming in a memory macro of an integrated circuit chip. It is assumed that all fails are row fails until determined to be bitline fails, circuits for implementing a method wherein it is assumed that all fails are row fails until determined to be bitline fails and test patterns are passed back to the failure detecting circuit when a wordline destination of the test patterns has previously been determined to be failing, and the test patterns and resultant patterns are passed between the memory macro and a test engine via logic paths connecting the memory macro to other circuits in said integrated circuit chip.Type: GrantFiled: March 12, 2008Date of Patent: May 31, 2011Assignee: International Business Machines CorporationInventors: John Edward Barth, Jr., Kevin William Gorman
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Patent number: 7920434Abstract: Techniques for sensing data states of respective memory cells in a memory array are provided, the memory array including at least a first bit line coupled to at least a subset of the memory cells. In one aspect, a circuit for sensing data states of respective memory cells in the memory array includes at least one sense amplifier coupled to the first bit line. The sense amplifier includes a first transistor operative to selectively inhibit charging of the first bit line in a manner which is independent of a voltage level on a second bit line coupled to the sense amplifier.Type: GrantFiled: August 27, 2008Date of Patent: April 5, 2011Assignee: International Business Machines CorporationInventors: Mesut Meterelliyoz, John Edward Barth, Jr., William Robert Reohr
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Publication number: 20100052026Abstract: A semiconductor structure is disclosed. The semiconductor structure includes an active semiconductor layer, a semiconductor device having a gate disposed on top of the active semiconductor layer, and source and drain regions and a body/channel region disposed within the active semiconductor layer, an insulator layer having a first and second side, the first side being adjacent to the active semiconductor layer, a substrate disposed adjacent to the second side of the insulator layer, a deep trench capacitor disposed under the body/channel region of the semiconductor device. The deep trench capacitor electrically connects with and contacts the body/channel region of the semiconductor device, and is located adjacent to the gate of the semiconductor device. The semiconductor structure increases a critical charge Qcrit, thereby reducing a soft error rate (SER) of the semiconductor device.Type: ApplicationFiled: August 28, 2008Publication date: March 4, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John Edward Barth, JR., Kerry Bernstein, Ethan Harrison Cannon, Francis Roger White
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Publication number: 20100054057Abstract: Techniques for sensing data states of respective memory cells in a memory array are provided, the memory array including at least a first bit line coupled to at least a subset of the memory cells. In one aspect, a circuit for sensing data states of respective memory cells in the memory array includes at least one sense amplifier coupled to the first bit line. The sense amplifier includes a first transistor operative to selectively inhibit charging of the first bit line in a manner which is independent of a voltage level on a second bit line coupled to the sense amplifier.Type: ApplicationFiled: August 27, 2008Publication date: March 4, 2010Inventors: Mesut Meterelliyoz, John Edward Barth, JR., William Robert Reohr
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Patent number: 7564729Abstract: A memory circuit includes multiple word lines, multiple pairs of complementary bank bit lines, multiple block select lines, and multiple of block circuits. Each of the block circuits includes a local bit line; a first transistor having a control terminal connected to the local bit line, a first bias terminal connected to a first bank bit line of a given pair of bank bit lines, and a second bias terminal connecting to a first voltage source; a second transistor having a control terminal connected to a corresponding one of the block select lines, a first bias terminal connected to a second bank bit line of the given pair of bank bit lines, and a second bias terminal connected to the local bit line; and a plurality of memory cells connected to the local bit line and to respective word lines in the memory circuit.Type: GrantFiled: March 27, 2008Date of Patent: July 21, 2009Assignee: International Business Machines CorporationInventors: John Edward Barth, Jr., Paul C. Parries, William Robert Reohr, Matthew R. Wordeman
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Patent number: 7549098Abstract: A method for implementing redundancy programming in a memory macro of an integrated circuit chip. It is assumed that all fails are row fails until determined to be bitline fails, test patterns are passed back to the failure detecting circuit when a wordline destination of the test patterns has previously been determined to be failing, and the test patterns and resultant patterns are passed between the memory macro and a test engine via logic paths connecting the memory macro to other circuits in said integrated circuit chip.Type: GrantFiled: December 19, 2006Date of Patent: June 16, 2009Assignee: International Business Machines CorporationInventors: John Edward Barth, Kevin William Gorman
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Publication number: 20080175085Abstract: A memory circuit includes multiple word lines, multiple pairs of complementary bank bit lines, multiple block select lines, and multiple of block circuits. Each of the block circuits includes a local bit line; a first transistor having a control terminal connected to the local bit line, a first bias terminal connected to a first bank bit line of a given pair of bank bit lines, and a second bias terminal connecting to a first voltage source; a second transistor having a control terminal connected to a corresponding one of the block select lines, a first bias terminal connected to a second bank bit line of the given pair of bank bit lines, and a second bias terminal connected to the local bit line; and a plurality of memory cells connected to the local bit line and to respective word lines in the memory circuit.Type: ApplicationFiled: March 27, 2008Publication date: July 24, 2008Applicant: International Business Machines CorporationInventors: John Edward Barth, Paul C. Parries, William Robert Reohr, Matthew R. Wordeman
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Publication number: 20080170448Abstract: A design structure for implementing redundancy programming in a memory macro of an integrated circuit chip. It is assumed that all fails are row fails until determined to be bitline fails, circuit means for implementing a method wherein it is assumed that all fails are row fails until determined to be bitline fails and test patterns are passed back to the failure detecting circuit when a wordline destination of the test patterns has previously been determined to be failing, and the test patterns and resultant patterns are passed between the memory macro and a test engine via logic paths connecting the memory macro to other circuits in said integrated circuit chip.Type: ApplicationFiled: March 12, 2008Publication date: July 17, 2008Inventors: John Edward Barth, Kevin William Gorman
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Publication number: 20080148114Abstract: A method for implementing redundancy programming in a memory macro of an integrated circuit chip. It is assumed that all fails are row fails until determined to be bitline fails, test patterns are passed back to the failure detecting circuit when a wordline destination of the test patterns has previously been determined to be failing, and the test patterns and resultant patterns are passed between the memory macro and a test engine via logic paths connecting the memory macro to other circuits in said integrated circuit chip.Type: ApplicationFiled: December 19, 2006Publication date: June 19, 2008Inventors: John Edward Barth, Kevin William Gorman
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Patent number: 7382672Abstract: A memory circuit includes multiple word lines, multiple pairs of complementary bank bit lines, multiple block select lines, and multiple of block circuits. Each of the block circuits includes a local bit line; a first transistor having a control terminal connected to the local bit line, a first bias terminal connected to a first bank bit line of a given pair of bank bit lines, and a second bias terminal connecting to a first voltage source; a second transistor having a control terminal connected to a corresponding one of the block select lines, a first bias terminal connected to a second bank bit line of the given pair of bank bit lines, and a second bias terminal connected to the local bit line; and a plurality of memory cells connected to the local bit line and to respective word lines in the memory circuit.Type: GrantFiled: May 29, 2007Date of Patent: June 3, 2008Assignee: International business Machines CorporationInventors: John Edward Barth, Jr., Paul C. Parries, William Robert Reohr, Matthew R. Wordeman
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Patent number: 7286385Abstract: A memory circuit includes multiple word lines, multiple pairs of complementary bank bit lines, multiple block select lines, and multiple of block circuits. Each of the block circuits includes a local bit line; a first transistor having a control terminal connected to the local bit line, a first bias terminal connected to a first bank bit line of a given pair of bank bit lines, and a second bias terminal connecting to a first voltage source; a second transistor having a control terminal connected to a corresponding one of the block select lines, a first bias terminal connected to a second bank bit line of the given pair of bank bit lines, and a second bias terminal connected to the local bit line; and a plurality of memory cells connected to the local bit line and to respective word lines in the memory circuit.Type: GrantFiled: July 27, 2005Date of Patent: October 23, 2007Assignee: International Business Machines CorporationInventors: John Edward Barth, Jr., Paul C. Parries, William Robert Reohr, Matthew R. Wordeman
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Publication number: 20050242414Abstract: An interlevel dielectric layer (ILD) comprises a low-k dielectric layer; and a low-k dielectric film, deposited under compressive stress, atop the dielectric layer. The dielectric layer comprises a low-k material, such as an organosilicon glass (OSG) or a SiCOH material. The dielectric film has a thickness, which is 2%-10% of the thickness of the dielectric layer, has a similar chemical composition to the dielectric layer, but has a different morphology than the dielectric layer. The dielectric film is deposited under compressive stress, in situ, at or near the end of the dielectric layer deposition by altering a process that was used to deposit the low-k dielectric layer.Type: ApplicationFiled: April 28, 2004Publication date: November 3, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Matthew Angyal, Edward Barth, Sanjit Das, Charles Davis, Habib Hichri, William Landers, Jia Lee
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Patent number: 6957372Abstract: An integrated circuit having a DRAM array connected to a power supply is tested for excessive current draw by selectively applying voltage to a single wordline or bitline, measuring current drawn, comparing the result with a reference number representing acceptable leakage, and replacing columns of the array having excessive leakage, thereby identifying and repairing latent defects that may become a cause of failure.Type: GrantFiled: August 26, 2002Date of Patent: October 18, 2005Assignees: International Business Machines Corporation, Infineon Technologies, AGInventors: John Edward Barth, Jr., Paul Christian Parries, Norman Whitelaw Robson
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Patent number: 6939797Abstract: An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a diffusion barrier or cap layer having a low dielectric constant (low-k), where the cap layer is formed of silicon nitride by a plasma-enhanced chemical vapor deposition (PE CVD) process. The metallization structure also includes an inter-layer dielectric (ILD) formed of a carbon-containing dielectric material having a dielectric constant of less than about 4, and a continuous hardmask layer overlying the ILD which is preferably formed of silicon nitride or silicon carbide. A method for forming the BEOL metallization structure is also disclosed. The method includes a pre-clean or pre-activation step to improve the adhesion of the cap layer to the underlying copper conductors. The pre-clean or pre-activation step comprises exposing the copper surface to a reducing plasma including hydrogen, ammonia, nitrogen and/or noble gases.Type: GrantFiled: November 12, 2003Date of Patent: September 6, 2005Assignee: International Business Machines CorporationInventors: Edward Barth, John A. Fitzsimmons, Stephen M. Gates, Thomas H. Ivers, Sarah L. Lane, Jia Lee, Ann McDonald, Vincent McGahay, Darryl D. Restaino
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Patent number: 6849563Abstract: The coating thickness and uniformity of spin-on deposition layers on semiconductor wafers is controlled through the in situ control of the viscosity and homogeneity of the mixture of precursor material and solvent material. The thickness of the deposited material is selected and the viscosity required at a given spin rate for the selected thickness is automatically mixed. Sensing and control apparatus are employed to ensure that the uniformity and viscosity required is maintained before dispensing onto said semiconductor wafer. Low-K dielectric materials of selected thickness are deposited in a uniform coating.Type: GrantFiled: December 9, 2002Date of Patent: February 1, 2005Assignee: International Business Machines CorporationInventors: Edward Barth, John A. Fitzsimmons, Arthur W. Martin, Lee M. Nicholson
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Patent number: 6791348Abstract: An integrated circuit having a charge pump is tested for excessive current draw by counting the number of times the charge pump cycles in a test interval, storing the result in a register that is used for another purpose during operation and comparing the result with a reference number representing acceptable leakage, thereby identifying latent defects that may become a cause of failure as well as short circuits.Type: GrantFiled: July 29, 2002Date of Patent: September 14, 2004Assignee: International Business Machines CorporationInventors: John Edward Barth, Jr., Paul Christian Parries
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Publication number: 20040173908Abstract: An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a diffusion barrier or cap layer having a low dielectric constant (low-k), where the cap layer is formed of silicon nitride by a plasma-enhanced chemical vapor deposition (PE CVD) process. The metallization structure also includes an inter-layer dielectric (ILD) formed of a carbon-containing dielectric material having a dielectric constant of less than about 4, and a continuous hardmask layer overlying the ILD which is preferably formed of silicon nitride or silicon carbide. A method for forming the BEOL metallization structure is also disclosed. The method includes a pre-clean or pre-activation step to improve the adhesion of the cap layer to the underlying copper conductors. The pre-clean or pre-activation step comprises exposing the copper surface to a reducing plasma including hydrogen, ammonia, nitrogen and/or noble gases.Type: ApplicationFiled: November 12, 2003Publication date: September 9, 2004Inventors: Edward Barth, John A. Fitzsimmons, Stephen M. Gates, Thomas H. Ivers, Sarah L. Lane, Jia Lee, Ann McDonald, Vincent McGahay, Darryl D. Restaino
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Publication number: 20040110394Abstract: The coating thickness and uniformity of spin-on deposition layers on semiconductor wafers is controlled through the in situ control of the viscosity and homogeneity of the mixture of precursor material and solvent material. The thickness of the deposited material is selected and the viscosity required at a given spin rate for the selected thickness is automatically mixed. Sensing and control apparatus are employed to ensure that the uniformity and viscosity required is maintained before dispensing onto said semiconductor wafer. Low-K dielectric materials of selected thickness are deposited in a uniform coating.Type: ApplicationFiled: December 9, 2002Publication date: June 10, 2004Applicant: International Business Machines CorporationInventors: Edward Barth, John A. Fitzsimmons, Arthur W. Martin, Lee M. Nicholson