Abstract: An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a diffusion barrier or cap layer having a low dielectric constant (low-k), where the cap layer is formed of silicon nitride by a plasma-enhanced chemical vapor deposition (PE CVD) process. The metallization structure also includes an inter-layer dielectric (ILD) formed of a carbon-containing dielectric material having a dielectric constant of less than about 4, and a continuous hardmask layer overlying the ILD which is preferably formed of silicon nitride or silicon carbide. A method for forming the BEOL metallization structure is also disclosed. The method includes a pre-clean or pre-activation step to improve the adhesion of the cap layer to the underlying copper conductors. The pre-clean or pre-activation step comprises exposing the copper surface to a reducing plasma including hydrogen, ammonia, nitrogen and/or noble gases.

Abstract: An integrated circuit having a DRAM array connected to a power supply is tested for excessive current draw by selectively applying voltage to a single wordline or bitline, measuring current drawn, comparing the result with a reference number representing acceptable leakage, and replacing columns of the array having excessive leakage, thereby identifying and repairing latent defects that may become a cause of failure.

Abstract: An integrated circuit having a charge pump is tested for excessive current draw by counting the number of times the charge pump cycles in a test interval, storing the result in a register that is used for another purpose during operation and comparing the result with a reference number representing acceptable leakage, thereby identifying latent defects that may become a cause of failure as well as short circuits.

Abstract: An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a diffusion barrier or cap layer having a low dielectric constant (low-k), where the cap layer is formed of silicon nitride by a plasma-enhanced chemical vapor deposition (PE CVD) process. The metallization structure also includes an inter-layer dielectric (ILD) formed of a carbon-containing dielectric material having a dielectric constant of less than about 4, and a continuous hardmask layer overlying the ILD which is preferably formed of silicon nitride or silicon carbide. A method for forming the BEOL metallization structure is also disclosed. The method includes a pre-clean or pre-activation step to improve the adhesion of the cap layer to the underlying copper conductors. The pre-clean or pre-activation step comprises exposing the copper surface to a reducing plasma including hydrogen, ammonia, nitrogen and/or noble gases.

Abstract: A method and apparatus for initializing an integrated circuit using compressed data from a remote fusebox allows a reduction in the number of fuses required to repair or customize an integrated circuit and allows fuses to be grouped outside of the macros repaired by the fuses. The remote location of fuses allows flexibility in the placement of macros having redundant repair capability, as well as a preferable grouping of fuses for both programming convenience and circuit layout facilitation. The fuses are arranged in rows and columns and represent control words and run-length compressed data to provide a greater quantity of repair points per fuse. The data can be loaded serially into shift registers and shifted to the macro locations to control the selection of redundant circuits to repair integrated circuits having defects or to customize logic.

Abstract: A method and apparatus for initializing an integrated circuit using compressed data from a remote fusebox allows a reduction in the number of fuses required to repair or customize an integrated circuit and allows fuses to be grouped outside of the macros repaired by the fuses. The remote location of fuses allows flexibility in the placement of macros having redundant repair capability, as well as a preferable grouping of fuses for both programming convenience and circuit layout facilitation. The fuses are arranged in rows and columns and represent control words and run-length compressed data to provide a greater quantity of repair points per fuse. The data can be loaded serially into shift registers and shifted to the macro locations to control the selection of redundant circuits to repair integrated circuits having defects or to customize logic.

Abstract: An integrated chip having a DRAM embedded in logic is tested by an in-situ processor oriented BIST macro. The BIST is provided with two ROMS, one for storing test instructions and a second, which is scannable, that provides sequencing for the test instructions stored in the first ROM, as well as branching and looping capabilities. The BIST macro has, in addition, a redundancy allocation logic section for monitoring failures within the DRAM and for replacing failing word and/or data lines. By stacking the DRAM in 0.5 mb increments up to a 4.0 mb maximum or in 1.0 mb increments up to an 8 mb maximum, all of which are controlled and tested by the BIST macro, a customized chip design with a high level of granularity can be achieved and tailored to specific applications within a larger ASIC.

Abstract: An integrated circuit chip with RAM, a RAM macro or bit slice data logic and at least one spare array element or spare slice element and the redundancy scheme therefor. The chip includes a wide data path with a plurality of interchangeable elements such as bit slice elements or memory element and at least one more element than the number of bits in the wide data path; selection logic for deselecting defective data elements; and, switches for selectively coupling each bit of the wide I/O data path to one element or to an element adjacent the one element responsive to the selection means. The integrated circuit chip may further include drive means for selectively driving data from the switches to the element or, otherwise, passing data from the elements to the switches. The switches preferably are three-way switches, such as three CMOS pass gates.

Abstract: A method for performing optical proximity correction is disclosed that not only limits the optical proximity correction to electrically relevant structures, but also improves the accuracy of the corrections by processing individual feature edges, and minimizes the mask manufacturing impacts by avoiding the introduction of jogs into the design. Critical edge regions of the relevant electrical structures are analyzed, sorted and manipulated to receive optical proximity corrections.

Abstract: A boundary independent decoder for a Synchronous Dynamic Random Access Memory (SDRAM) with an n bit burst transfer block length. A user, usually a processor or microprocessor requests access to a block of SDRAM memory. The requested block may begin between array decode boundaries. A column address is decoded by an SDRAM column decoder. The decoder selects a starting boundary for 2n bits. The first requested bit is in the first n bits of the 2n selected bits. Thus, the entire n bit block is included in the selected 2n bit block. The n bit block is selected from the selected 2n bits and latched in a high speed decoder/register in a sequentially scrambled order, i.e., the i.sup.th bit is the first requested bit and the requested bit order is i, . . . , (n-1), . . . , 0, . . . , (i-1). Latched data is scrambled either sequentially or interleaved, if required. Scrambled data is burst transferred off chip.