Abstract: The present invention provides for recombinant antibodies having the features of ruminant early colostrum antibodies that impart resistance to proteases and intestinal digestion. It is a feature of the present invention that when administered to animals including humans, pharmaceutical compositions comprising the novel recombinant antibodies of the present invention, advantageously exhibit resistance to proteases and intestinal digestion. Thus, pharmaceutical compositions of the recombinant antibodies of the invention may be used to deliver antibody therapeutics particularly by oral delivery to the gastrointestinal tract when oral delivery is advantageous.

Abstract: The present invention provides for recombinant antibodies having the features of ruminant early colostrum antibodies that impart resistance to proteases and intestinal digestion. It is a feature of the present invention that when administered to animals including humans, pharmaceutical compositions comprising the novel recombinant antibodies of the present invention, advantageously exhibit resistance to proteases and intestinal digestion. Thus, pharmaceutical compositions of the recombinant antibodies of the invention may be used to deliver antibody therapeutics particularly by oral delivery to the gastrointestinal tract when oral delivery is advantageous.

Abstract: An actuator component for a droplet ejection head; wherein said actuator component comprises a substrate and one or more strips of piezoelectric material fixedly attached to said substrate; wherein said one or more strips of piezoelectric material comprise one or more layers of piezoelectric material, and an array of fluid chambers defined within said one or more strips of piezoelectric material and extending in an array direction; wherein said actuator component further comprises one or more cover parts; wherein the or each cover part extends in said array direction and is fixedly attached to at least one of a side face of one of said strips of piezoelectric material and/or at least a portion of said substrate; and wherein said one or more cover parts comprise a plurality of openings so as to enable fluid to be supplied to selected ones of said fluid chambers through said openings. Associated methods of manufacturing an actuator component for a droplet ejection head are also provided.

Abstract: Stacked semiconductor die architectures having one or more base dies and techniques of forming such architectures are described. The stacked semiconductor die architectures may be included in or used to form semiconductor packages. A stacked semiconductor die architecture can include: (i) one or more base dies (e.g., at least one disaggregated base die, at least one monolithic base die, etc.); and (ii) a carrier wafer having multiple stacked semiconductor dies embedded in the carrier wafer, where the carrier wafer is on the one or more base dies and where one or more interconnect structures (e.g., wires, bumps, microbumps, pillars, etc.) couple the one or more base dies to the carrier wafer and/or the stacked semiconductor dies.

Abstract: Stacked semiconductor die architectures having one or more base dies and techniques of forming such architectures are described. The stacked semiconductor die architectures may be included in or used to form semiconductor packages. A stacked semiconductor die architecture can include: (i) one or more base dies (e.g., at least one disaggregated base die, at least one monolithic base die, etc.); and (ii) a carrier wafer having multiple stacked semiconductor dies embedded in the carrier wafer, where the carrier wafer is on the one or more base dies and where one or more interconnect structures (e.g., wires, bumps, microbumps, pillars, etc.) couple the one or more base dies to the carrier wafer and/or the stacked semiconductor dies.

Abstract: A method for providing container flooring for a container, including: providing a plurality of container flooring boards, each including a plurality of strand layers including strands of wood bonded together, at least a top strand layer and a bottom strand layer of the container flooring board having its strands substantially aligned in a first direction, and a dimension of the container flooring board in a second direction that is perpendicular to the first direction being selected to extend laterally between sides of the container in use; and arranging the container flooring boards inside the container, each container flooring board being positioned so that the strands of the top strand layer and the bottom strand layer are substantially aligned longitudinally relative to the container and the container flooring board extends laterally between the sides of the container, and respective edges of adjacent container flooring boards abut one another.

Abstract: An apparatus and method is described that digitally coordinates dynamically adaptable clock and voltage supply to significantly reduce the energy consumed by a processor without impacting its performance or latency. A signal is generated that indicates a long latency operation. This signal is used to reduce power supply voltage and frequency of the adaptable clock. An early resume indicator is generated a few nanoseconds before normal operations are about to resume. This early resume signal is used to power up the power-downed voltage regulator, and/or can increase frequency and/or supply voltage back to normal level before normal processor operations are about to resume.

Abstract: Various embodiments provide a parallel arrangement of discontinuous conduction mode (DCM) voltage regulators to provide a regulated voltage to a load. The individual DCM voltage regulators may be triggered (e.g., switched to a charge state) when the regulated voltage falls below a lower threshold. Different DCM voltage regulators in the parallel arrangement may have different lower thresholds. In some embodiments, different DCM voltage regulators may include different inductance and/or transistor size (e.g., to tune the DCM voltage regulators to different current handling capabilities). Other embodiments may be described and claimed.

Abstract: A vanadium recovery process (10), the process comprising: (i) passing an ore or concentrate (12) containing vanadium, titanium and iron to a reduction step (18) forming a reduced ore or concentrate; (ii) passing the reduced ore or concentrate to a ferric leach step (22) to produce a ferric leachate (26) containing iron and a ferric leach residue (30) containing vanadium; (iii) passing the ferric leachate (26) to a ferric oxidation step (28) producing an iron product (68); (iv) passing the ferric leach residue (30) to an acid leach step (32) producing an acid leachate (44) containing vanadium and an acid leach residue (36) containing titanium; (v) Passing the acid leachate (44) to a vanadium recovery step (46, 48) from which a vanadium product is produced; and (vi) Passing the acid leach residue (36) to a titanium pigment production process (42) whereby a titanium dioxide pigment is produced.

Abstract: A computing chip can include one or more voltage regulators to decrease a standard voltage, such as twelve volts, to a relatively low operating voltage of its processing cores, typically around one volt. Because the power consumed by the cores can be substantial, such as three hundred watts or more, it is desirable to locate the voltage regulators as close as possible to the cores, to reduce the distances that relatively large currents have to travel in the chip circuitry. The voltage regulators can be embedded within the package, such as in a layered structure, in a layer that electrically connects to the cores. While the cores are typically manufactured using the smallest possible lithographic features, the voltage regulators are less demanding and can instead use relatively large lithographic features, which can be formed using relatively old technology, and can therefore be relatively inexpensive.

Abstract: A dual-loop low-drop (LDO) regulator having a first loop which is an analog loop that compares the voltage on the output supply node with a reference, and generates a bias or voltage control to control a strength of a final power switch. The first loop regulates the output voltage relative to a reference voltage by minimizing the error between the two voltages. A second loop (digital loop) that controls a current source which injects current on the gate of the final power switch to boost current for a load. The second loop is an auxiliary loop that boosts the current load for a set interval until the tracking bandwidth of the LDO resolves the error in the output, thereby reducing the peak-to-peak noise. The quiescent current is not increased a lot by the second loop since the second loop circuit is on for a fraction of the entire LDO operation.

Abstract: An integrated circuit (IC) package, comprising a substrate that comprises a bridge die embedded within a dielectric. A first die comprising a first input/output (I/O) transmitter and a second die comprising a second I/O receiver and electrically coupled to the bridge die. A first signal trace and a first power conductor are within the bridge die. The first signal trace and the first power conductor are electrically coupled to the first I/O transmitter and the second I/O receiver. The first signal trace is to carry a digital signal and the first power conductor to provide a voltage for the second I/O receiver to read the digital signal.

Abstract: The present invention provides for recombinant antibodies having the features of ruminant early colostrum antibodies that impart resistance to proteases and intestinal digestion. It is a feature of the present invention that when administered to animals including humans, pharmaceutical compositions comprising the novel recombinant antibodies of the present invention, advantageously exhibit resistance to proteases and intestinal digestion. Thus, pharmaceutical compositions of the recombinant antibodies of the invention may be used to deliver antibody therapeutics particularly by oral delivery to the gastrointestinal tract when oral delivery is advantageous.

Abstract: A mesh interconnect interface includes a dielectric slice; first micro-bumps aligned along a longitudinal axis and positioned closest to a driver bank, which is to be coupled to a first mesh stop of a first chiplet; second micro-bumps similarly aligned and positioned farthest from the first driver bank; third micro-bumps similarly aligned and positioned closest to a second driver bank, which is to be coupled to a second mesh stop of a second chiplet; fourth micro-bumps similarly aligned and positioned farthest from the second driver bank, wherein the longitudinal axis is orthogonal to a gap between the chiplets. The groups of micro-bumps are disposed on the slice. A first group of wires are embedded in the slice to couple the first and second micro-bumps. A second group of wires are interleaved with the first group of wires and embedded in the slice to couple the second and third micro-bumps.

Abstract: Techniques are described for fabricating integrated circuit devices that span multiple reticle fields. Integrated circuits formed within separate reticle fields are placed into electrical contact with each other by overlapping reticle fields to form an overlapping conductive interconnect. This overlapping conductive interconnect electrically connects an interconnect layer of a first reticle field with an interconnect layer of a second, laterally adjacent reticle field. The overlapping conductive interconnection extends into a common scribe zone between adjacent reticle fields.

Abstract: An apparatus and method is described that digitally coordinates dynamically adaptable clock and voltage supply to significantly reduce the energy consumed by a processor without impacting its performance or latency. A signal is generated that indicates a long latency operation. This signal is used to reduce power supply voltage and frequency of the adaptable clock. An early resume indicator is generated a few nanoseconds before normal operations are about to resume. This early resume signal is used to power up the power-downed voltage regulator, and/or can increase frequency and/or supply voltage back to normal level before normal processor operations are about to resume.

Abstract: A computing chip can include one or more voltage regulators to decrease a standard voltage, such as twelve volts, to a relatively low operating voltage of its processing cores, typically around one volt. Because the power consumed by the cores can be substantial, such as three hundred watts or more, it is desirable to locate the voltage regulators as close as possible to the cores, to reduce the distances that relatively large currents have to travel in the chip circuitry. The voltage regulators can be embedded within the package, such as in a layered structure, in a layer that electrically connects to the cores. While the cores are typically manufactured using the smallest possible lithographic features, the voltage regulators are less demanding and can instead use relatively large lithographic features, which can be formed using relatively old technology, and can therefore be relatively inexpensive.

Abstract: Various embodiments provide a parallel arrangement of discontinuous conduction mode (DCM) voltage regulators to provide a regulated voltage to a load. The individual DCM voltage regulators may be triggered (e.g., switched to a charge state) when the regulated voltage falls below a lower threshold. Different DCM voltage regulators in the parallel arrangement may have different lower thresholds. In some embodiments, different DCM voltage regulators may include different inductance and/or transistor size (e.g., to tune the DCM voltage regulators to different current handling capabilities). Other embodiments may be described and claimed.

Abstract: A computing chip can include one or more voltage regulators to decrease a standard voltage, such as twelve volts, to a relatively low operating voltage of its processing cores, typically around one volt. Because the power consumed by the cores can be substantial, such as three hundred watts or more, it is desirable to locate the voltage regulators as close as possible to the cores, to reduce the distances that relatively large currents have to travel in the chip circuitry. The voltage regulators can be embedded within the package, such as in a layered structure, in a layer that electrically connects to the cores. While the cores are typically manufactured using the smallest possible lithographic features, the voltage regulators are less demanding and can instead use relatively large lithographic features, which can be formed using relatively old technology, and can therefore be relatively inexpensive.

Abstract: A computing chip can include one or more voltage regulators to decrease a standard voltage, such as twelve volts, to a relatively low operating voltage of its processing cores, typically around one volt. Because the power consumed by the cores can be substantial, such as three hundred watts or more, it is desirable to locate the voltage regulators as close as possible to the cores, to reduce the distances that relatively large currents have to travel in the chip circuitry. The voltage regulators can be embedded within the package, such as in a layered structure, in a layer that electrically connects to the cores. While the cores are typically manufactured using the smallest possible lithographic features, the voltage regulators are less demanding and can instead use relatively large lithographic features, which can be formed using relatively old technology, and can therefore be relatively inexpensive.