Patents by Inventor Edward Burton

Edward Burton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10643984
    Abstract: A computing chip can include one or more voltage regulators to decrease a standard voltage, such as twelve volts, to a relatively low operating voltage of its processing cores, typically around one volt. Because the power consumed by the cores can be substantial, such as three hundred watts or more, it is desirable to locate the voltage regulators as close as possible to the cores, to reduce the distances that relatively large currents have to travel in the chip circuitry. The voltage regulators can be embedded within the package, such as in a layered structure, in a layer that electrically connects to the cores. While the cores are typically manufactured using the smallest possible lithographic features, the voltage regulators are less demanding and can instead use relatively large lithographic features, which can be formed using relatively old technology, and can therefore be relatively inexpensive.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: May 5, 2020
    Assignee: Intel Corporation
    Inventor: Edward A. Burton
  • Patent number: 10635155
    Abstract: Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: April 28, 2020
    Assignee: Intel Corporation
    Inventors: Stephen H. Gunther, Edward A. Burton, Anant Deval, Stephan Jourdan, Robert Greiner, Michael Cornaby
  • Patent number: 10613610
    Abstract: Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: April 7, 2020
    Assignee: Intel Corporation
    Inventors: Stephen H. Gunther, Edward A. Burton, Anant Deval, Stephan Jourdan, Robert Greiner, Michael Cornaby
  • Publication number: 20200105733
    Abstract: A computing chip can include one or more voltage regulators to decrease a standard voltage, such as twelve volts, to a relatively low operating voltage of its processing cores, typically around one volt. Because the power consumed by the cores can be substantial, such as three hundred watts or more, it is desirable to locate the voltage regulators as close as possible to the cores, to reduce the distances that relatively large currents have to travel in the chip circuitry. The voltage regulators can be embedded within the package, such as in a layered structure, in a layer that electrically connects to the cores. While the cores are typically manufactured using the smallest possible lithographic features, the voltage regulators are less demanding and can instead use relatively large lithographic features, which can be formed using relatively old technology, and can therefore be relatively inexpensive.
    Type: Application
    Filed: September 28, 2018
    Publication date: April 2, 2020
    Inventor: Edward A. Burton
  • Publication number: 20200066651
    Abstract: Techniques are described for fabricating integrated circuit devices that span multiple reticle fields. Integrated circuits formed within separate reticle fields are placed into electrical contact with each other by overlapping reticle fields to form an overlapping conductive interconnect. This overlapping conductive interconnect electrically connects an interconnect layer of a first reticle field with an interconnect layer of a second, laterally adjacent reticle field. The overlapping conductive interconnection extends into a common scribe zone between adjacent reticle fields.
    Type: Application
    Filed: June 29, 2017
    Publication date: February 27, 2020
    Applicant: INTEL CORPORATION
    Inventors: Edward A. Burton, Mark T. Bohr, Murray Fitzpatrick Kelley, Shawn Michael Klauser
  • Patent number: 10534419
    Abstract: Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: January 14, 2020
    Assignee: Intel Corporation
    Inventors: Stephen H. Gunther, Edward A. Burton, Anant Deval, Stephan Jourdan, Robert Greiner, Michael Cornaby
  • Publication number: 20190377405
    Abstract: In some examples, a voltage protection apparatus includes a circuit to compare an input voltage of a processor to a threshold voltage, and to provide a throttle signal to the processor if the input voltage of the processor droops below the threshold voltage. The processor input voltage can then be set to a lower voltage and the processor power can thus be lowered.
    Type: Application
    Filed: March 29, 2019
    Publication date: December 12, 2019
    Applicant: Intel Corporation
    Inventors: Alexander B. Uan-Zo-li, Eugene Gorbatov, Philip R. Lehwalder, Michael Zelikson, Sameer Shekhar, Nimrod Angel, Jonathan Douglas, Muhammad Abozaed, Alan Hallberg, Douglas Huard, Edward Burton, Merwin Brown
  • Patent number: 10483249
    Abstract: Embodiments are generally directed to integrated passive devices on chip. An embodiment of a device includes a semiconductor die; a semiconductor die package, a first side of the package being coupled with the semiconductor die; and one or more separate dies to provide passive components for operation of the semiconductor die, wherein the passive components for operation of the semiconductor die includes inductors.
    Type: Grant
    Filed: December 26, 2015
    Date of Patent: November 19, 2019
    Assignee: Intel Corporation
    Inventors: Donald S. Gardner, Edward A. Burton, Gerhard Schrom, Larry E. Mosley
  • Publication number: 20190245582
    Abstract: A mesh interconnect interface includes a dielectric slice; first micro-bumps aligned along a longitudinal axis and positioned closest to a driver bank, which is to be coupled to a first mesh stop of a first chiplet; second micro-bumps similarly aligned and positioned farthest from the first driver bank; third micro-bumps similarly aligned and positioned closest to a second driver bank, which is to be coupled to a second mesh stop of a second chiplet; fourth micro-bumps similarly aligned and positioned farthest from the second driver bank, wherein the longitudinal axis is orthogonal to a gap between the chiplets. The groups of micro-bumps are disposed on the slice. A first group of wires are embedded in the slice to couple the first and second micro-bumps. A second group of wires are interleaved with the first group of wires and embedded in the slice to couple the second and third micro-bumps.
    Type: Application
    Filed: April 15, 2019
    Publication date: August 8, 2019
    Inventor: Edward Burton
  • Patent number: 10374198
    Abstract: An organic field effect transistor includes a semiconductor substrate having an insulating layer and a source electrode and a drain electrode located on the insulating layer, where the source electrode and drain electrode are spaced apart and define a channel region. The organic field effect transistor also includes an organic semiconductor located in the channel region.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: August 6, 2019
    Assignee: Georgetown University
    Inventors: Edward Van Keuren, George Burton
  • Patent number: 10354786
    Abstract: Embodiments are generally directed to hybrid magnetic material structures for electronic devices and circuits. An embodiment of an inductor includes a first layer of magnetic film material applied on a substrate, one or more conductors placed on the first layer of magnetic film material, and a second layer of magnetic particles, wherein the magnetic particles are suspended in an insulating medium.
    Type: Grant
    Filed: October 1, 2016
    Date of Patent: July 16, 2019
    Assignee: Intel Corporation
    Inventors: Donald S. Gardner, Gerhard Schrom, Edward A. Burton
  • Publication number: 20190206836
    Abstract: Stacked semiconductor die architectures having thermal spreaders disposed between stacked semiconductor dies and techniques of forming such architectures are described. The stacked semiconductor die architectures may be included in or used to form semiconductor packages. A stacked semiconductor die architecture can include: (i) a base die; (ii) a plurality of stacked semiconductor dies arranged on the base die; and (iii) at least one thermal spreader disposed in one or more gaps between the plurality of stacked semiconductor dies or in one or more areas on the base die that are adjacent to the plurality of stacked semiconductor dies. The thermal spreaders can assist with thermal management of the dies, which can assist with improving the power density of the stacked semiconductor die architecture. At least one other stacked semiconductor die architecture s also described.
    Type: Application
    Filed: December 30, 2017
    Publication date: July 4, 2019
    Inventor: Edward A. BURTON
  • Patent number: 10322571
    Abstract: A lamination cassette includes a substrate to accommodate a plurality of first sheets of a first size. A loading template is removably coupled to the cassette via an adapter on the cassette to secure the loading template when inclined for loading. The template includes a first loading section for accommodating a plurality of second sheets of a second size smaller than the first size when loaded onto the substrate. The lamination cassette is configured to support sheets of the first size when the adapter is not coupled to the substrate and the vertical support surface is configured to support sheets of the second size when the loading template is coupled to the substrate. The loading template may also include a second loading section for accommodating a plurality of third sheets having the same size as the second sheets for laminating two pluralities of same size sheets on a single cassette.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: June 18, 2019
    Assignee: GIESECKE+DEVRIENT MOBILE SECURITY AMERICA, INC.
    Inventors: Christopher William Burton, Daniel William Hunt, David Edward Boelens
  • Patent number: 10315558
    Abstract: A locking position stud fastener is configured to position, lock, and securely hold a lamp assembly to a vehicle body. A method for installing a lamp assembly on to a vehicle body having at least one opening for receiving a fastener includes the steps of securing a first end of a stud to the lamp assembly, rotating the stud about its axis, passing the stud through the vehicle body opening, and then locking and securing the stud in the vehicle body.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: June 11, 2019
    Assignee: Burton Technologies, LLC
    Inventor: John Edwards Burton
  • Patent number: 10319700
    Abstract: Stacked semiconductor die architectures having thermal spreaders disposed between stacked semiconductor dies and techniques of forming such architectures are described. The stacked semiconductor die architectures may be included in or used to form semiconductor packages. A stacked semiconductor die architecture can include: (i) a base die; (ii) a plurality of stacked semiconductor dies arranged on the base die; and (iii) at least one thermal spreader disposed in one or more gaps between the plurality of stacked semiconductor dies or in one or more areas on the base die that are adjacent to the plurality of stacked semiconductor dies. The thermal spreaders can assist with thermal management of the dies, which can assist with improving the power density of the stacked semiconductor die architecture. At least one other stacked semiconductor die architecture s also described.
    Type: Grant
    Filed: December 30, 2017
    Date of Patent: June 11, 2019
    Assignee: Intel Corporation
    Inventor: Edward A. Burton
  • Patent number: 10301909
    Abstract: An actuation system and method, the system including a tubular having a passage, and an assembly disposed with the tubular. The assembly includes a degradable restriction, the restriction only partially blocking the passage prior to being degraded. The assembly is configured to receive and prevent further movement of a restrictor through the tubular prior to the restriction being degraded. The assembly is further configured to release the restrictor when the restriction is degraded.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: May 28, 2019
    Assignee: BAKER HUGHES, A GE COMPANY, LLC
    Inventors: Matthew T. McCoy, Matthew D. Solfronk, Jack D. Farmer, William A. Burton, James G. King, Jason J. Barnard, Edward J. O'Malley
  • Publication number: 20190006334
    Abstract: Embodiments are generally directed to integrated passive devices on chip. An embodiment of a device includes a semiconductor die; a semiconductor die package, a first side of the package being coupled with the semiconductor die; and one or more separate dies to provide passive components for operation of the semiconductor die, wherein the passive components for operation of the semiconductor die includes inductors.
    Type: Application
    Filed: December 26, 2015
    Publication date: January 3, 2019
    Inventors: Donald S. GARDNER, Edward A. BURTON, Gerhard SCHROM, Larry E. MOSLEY
  • Patent number: 10095300
    Abstract: Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: October 9, 2018
    Assignee: Intel Corporation
    Inventors: Stephen H. Gunther, Edward A. Burton, Anant Deval, Stephan Jourdan, Robert Greiner, Michael Cornaby
  • Publication number: 20180232039
    Abstract: Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.
    Type: Application
    Filed: April 12, 2018
    Publication date: August 16, 2018
    Inventors: Stephen H. Gunther, Edward A. Burton, Anant Deval, Stephan Jourdan, Robert Greiner, Michael Cornaby
  • Publication number: 20180232041
    Abstract: Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.
    Type: Application
    Filed: April 12, 2018
    Publication date: August 16, 2018
    Inventors: Stephen H. Gunther, Edward A. Burton, Anant Deval, Stephan Jourdan, Robert Greiner, Michael Cornaby