Patents by Inventor Edward Burton

Edward Burton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8446883
    Abstract: A method and system for the networking of radio transceivers is disclosed. The system includes a source transceiver with a source address, and a destination transceiver with a destination address. A router gateway includes a first interface in communication with the source transceiver and a second interface in communication with the destination transceiver, and interconnections between the two are defined in a routing table. A network signaling system independent of the respective radio transmission and receipt systems enables communication between the source transceiver and the destination transceiver.
    Type: Grant
    Filed: September 16, 2009
    Date of Patent: May 21, 2013
    Assignee: Northrop Grumman Corporation
    Inventors: Michael Thomas Curtin, Dale Edward Burton
  • Patent number: 8418569
    Abstract: A variable torque-rate test point for the performance testing of rotary tools for threaded fasteners comprises a screw-threaded bolt (1) having a moment of inertia comparable to that of a bolt to be tightened using the rotary tool. The bolt (1) is tightened in the test joint against a torque-rate adjustment device (6) which can be adjusted to simulate a hard or a soft joint. The adjustment device (6) comprises a washer portion (7) beneath the bolt head (4), at least one spring beam (8) extending from a reaction point (9) radially outwardly of the bolt (1), and a pivotal bearing member (10) or other pivot at a mid portion of the beam (8). The beam (8) flexes as it extends in cantilever over the pivot point, and that flexure can be adjusted to vary the torque-rate of the test joint by varying the distance between the pivot point and the rotary axis of the bolt (1).
    Type: Grant
    Filed: April 11, 2008
    Date of Patent: April 16, 2013
    Inventors: Peter William Everitt, Ben William Tyers, Andrew Chapman, John Edward Burton
  • Patent number: 8402294
    Abstract: A central processing unit (CPU) is disclosed. The CPU includes two or more processing cores and a power control unit to regulate voltage applied to the CPU based upon the number of processing cores that are active.
    Type: Grant
    Filed: December 21, 2009
    Date of Patent: March 19, 2013
    Assignee: Intel Corporation
    Inventor: Edward Burton
  • Patent number: 8397090
    Abstract: Methods and apparatus to operate various logic blocks of an integrated circuit (IC) at independent voltages are described. In one embodiment, supply of power to one or more domains in an IC is adjusted based on an indication that power consumption by components of the corresponding domain is to be modified. Other embodiments are also described.
    Type: Grant
    Filed: December 8, 2006
    Date of Patent: March 12, 2013
    Assignee: Intel Corporation
    Inventors: Stephen H. Gunther, Edward Burton, Anant Deval, Stephan Jourdan, Robert Greiner, Mike Cornaby
  • Publication number: 20130036835
    Abstract: The invention provides a variable torque-rate test joint for the performance testing of rotary tools for threaded fasteners. In a typical test routine a nut is repeatedly tightened by the tool and after each tightening the nut must be released and run back to its start position. The invention provides a means for rapidly releasing the pressure on the tightened nut so that it can be run back quickly and easily. The variable joint is supported by a reaction surface that is the operative face of a piston and cylinder assembly seated on a shoulder fast to a shank of the threaded fastener. A hydraulic control is provided for the piston and cylinder assembly including means for hydraulically extending the piston from the cylinder to a fixed maximum extension which defines a test position of the reaction surface, and means for hydraulically retracting the piston back into the cylinder to remove the pressure from the nut at the end of the test.
    Type: Application
    Filed: January 10, 2011
    Publication date: February 14, 2013
    Applicant: Crane Electronics Ltd.
    Inventors: Peter William Everitt, John Edward Burton
  • Patent number: 8373074
    Abstract: An inductor and multiple inductors embedded in a substrate (e.g., IC package substrate, board substrate, and/or other substrate) is provided herein.
    Type: Grant
    Filed: November 3, 2009
    Date of Patent: February 12, 2013
    Assignee: Intel Corporation
    Inventors: Peter Hazucha, Edward Burton, Trang T. Nguyen, Gerhard Schrom, Fabrice Paillet, Kaladhar Radhakrishnan, Donald S. Gardner, Sung T. Moon, Tanay Karnik
  • Publication number: 20120239946
    Abstract: Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.
    Type: Application
    Filed: June 1, 2012
    Publication date: September 20, 2012
    Inventors: Stephen Gunther, Edward A. Burton, Anant Deval, Stephen Jourdan, Robert Greiner, Michael Cornaby
  • Publication number: 20120226926
    Abstract: Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.
    Type: Application
    Filed: May 14, 2012
    Publication date: September 6, 2012
    Inventors: Stephen H. Gunther, Edward A. Burton, Anant Deval, Stephan Jourdan, Robert Greiner, Michael Cornaby
  • Patent number: 8214677
    Abstract: A system is disclosed. The system includes a central processing unit (CPU) to operate in one or more low power sleep states, and a power converter. The power converter includes phase inductors; and one or more power switches to drive the phase inductors. The one or more power switches are deactivated during the CPU sleep state.
    Type: Grant
    Filed: July 13, 2009
    Date of Patent: July 3, 2012
    Assignee: Intel Corporation
    Inventors: Edward Burton, Robert Greiner, Anat Deval, Doug Huard
  • Patent number: 8101251
    Abstract: A water release agent that release water over an application temperature range in an amount sufficient to cure a composition is add to a curable composition containing 10 to 65 weight % of a moisture-curable, silane-functional, elastomeric, organic polymer; 0.1 to 3 weight % of a condensation catalyst; and (C) 15 to 25 weight % of a physical drying agent. When used as an edge-seal in an IG unit, the cured product of the composition performs the functions of sealing, bonding, spacing, and desiccating.
    Type: Grant
    Filed: June 25, 2007
    Date of Patent: January 24, 2012
    Assignee: Dow Corning Corporation
    Inventors: Edward Burton Scott, Andreas Thomas Wolf
  • Publication number: 20110291441
    Abstract: A cross laminated strand product formed from a laminate of a plurality of layers, wherein each layer includes substantially aligned strands of wood bonded together with a binder including an isocyanate resin, and wherein the respective strands of adjacent layers are oriented substantially perpendicularly to one another.
    Type: Application
    Filed: May 26, 2011
    Publication date: December 1, 2011
    Applicant: LIGNOR LIMITED
    Inventor: Peter Edward BURTON
  • Patent number: 8069358
    Abstract: Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.
    Type: Grant
    Filed: August 21, 2009
    Date of Patent: November 29, 2011
    Assignee: Intel Corporation
    Inventors: Stephen H. Gunther, Edward A. Burton, Anant Deval, Stephan Jourdan, Robert Greiner, Michael Cornaby
  • Patent number: 8037326
    Abstract: Methods and apparatuses provide voltage regulation for a processor. Control or configuration parameters for a voltage regulator (VR) are provided digitally over a configuration bus to a VR controller. The parameters may be provided directly from a storage element, or via a processing element or processor core. Based in whole or in part on the parameters, the VR controller provides an output control signal to affect a power output from a power converter to the processing element. In one embodiment, the VR controller is integrated onto the same IC as the processing element.
    Type: Grant
    Filed: February 2, 2010
    Date of Patent: October 11, 2011
    Assignee: Intel Corporation
    Inventors: Edward A. Burton, Robert J. Greiner, Anant S. Deval, Douglas R. Huard, Jeremy J. Shrall, Arun R. Ramadorai, Benson D. Inkley, Martin M. Chang
  • Patent number: 7999607
    Abstract: Power switch units for microelectronic devices are disclosed. In one aspect, a microelectronic device may include a functional circuit, and a power switch unit to switch power to the functional circuit on and off. The power switch unit may include a large number of transistors coupled together. The transistors may include predominantly positive-channel, insulated gate field effect transistors, which have a gate dielectric that includes a high dielectric constant material. Power switch units having such transistors may tend to have low power consumption. In an aspect, an overdrive voltage may be applied to the gates of such transistors to further reduce power consumption. Methods of overdriving such transistors and systems including such power switch units are also disclosed.
    Type: Grant
    Filed: May 6, 2010
    Date of Patent: August 16, 2011
    Assignee: Intel Corporation
    Inventors: Kelin J. Kuhn, Richard K. Hose, Jr., Edward Burton, Rajesh Kumar
  • Publication number: 20110191607
    Abstract: Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.
    Type: Application
    Filed: April 14, 2011
    Publication date: August 4, 2011
    Inventors: Stephen H. Gunther, Edward A. Burton, Anant Deval, Stephan Jourdan, Robert Greiner, Michael Cornaby
  • Patent number: 7949887
    Abstract: Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.
    Type: Grant
    Filed: November 1, 2006
    Date of Patent: May 24, 2011
    Assignee: Intel Corporation
    Inventors: Stephen H. Gunther, Edward A. Burton, Anant Deval, Stephan Jourdan, Robert Greiner, Michael Cornaby
  • Publication number: 20110064022
    Abstract: A method and system for the networking of radio transceivers is disclosed. The system includes a source transceiver with a source address, and a destination transceiver with a destination address. A router gateway includes a first interface in communication with the source transceiver and a second interface in communication with the destination transceiver, and interconnections between the two are defined in a routing table. A network signaling system independent of the respective radio transmission and receipt systems enables communication between the source transceiver and the destination transceiver.
    Type: Application
    Filed: September 16, 2009
    Publication date: March 17, 2011
    Inventors: Michael Thomas Curtin, Dale Edward Burton
  • Patent number: 7886167
    Abstract: For one disclosed embodiment, an apparatus comprises a load circuit having one or more memory devices, one or more temperature sensors to sense one or more temperatures for the load circuit, and supply voltage control circuitry to control supply voltage to be applied to the load circuit. The supply voltage control circuitry may vary the supply voltage based at least in part on one or more sensed temperatures when the load circuit is in an inactive state and may help retain one or more signals by one or more memory devices of the load circuit as the supply voltage is varied. Other embodiments are also disclosed.
    Type: Grant
    Filed: May 11, 2006
    Date of Patent: February 8, 2011
    Assignee: Intel Corporation
    Inventor: Edward Burton
  • Publication number: 20110022865
    Abstract: Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.
    Type: Application
    Filed: October 6, 2010
    Publication date: January 27, 2011
    Inventors: Stephen H. Gunther, Edward A. Burton, Anant Deval, Stephan Jourdan, Robert Greiner, Michael Cornaby
  • Publication number: 20100266807
    Abstract: A hard wood strand lumber or board product including strands of one or more eucalypts bonded together with a binder including an isocyanate resin.
    Type: Application
    Filed: May 7, 2010
    Publication date: October 21, 2010
    Applicant: LIGNOR LIMITED
    Inventors: Peter Edward BURTON, Graham Thomas COULTHARD