Abstract: Stacked semiconductor die architectures having one or more base dies and techniques of forming such architectures are described. The stacked semiconductor die architectures may be included in or used to form semiconductor packages. A stacked semiconductor die architecture can include: (i) one or more base dies (e.g., at least one disaggregated base die, at least one monolithic base die, etc.); and (ii) a carrier wafer having multiple stacked semiconductor dies embedded in the carrier wafer, where the carrier wafer is on the one or more base dies and where one or more interconnect structures (e.g., wires, bumps, microbumps, pillars, etc.) couple the one or more base dies to the carrier wafer and/or the stacked semiconductor dies.

Abstract: A computing chip can include one or more voltage regulators to decrease a standard voltage, such as twelve volts, to a relatively low operating voltage of its processing cores, typically around one volt. Because the power consumed by the cores can be substantial, such as three hundred watts or more, it is desirable to locate the voltage regulators as close as possible to the cores, to reduce the distances that relatively large currents have to travel in the chip circuitry. The voltage regulators can be embedded within the package, such as in a layered structure, in a layer that electrically connects to the cores. While the cores are typically manufactured using the smallest possible lithographic features, the voltage regulators are less demanding and can instead use relatively large lithographic features, which can be formed using relatively old technology, and can therefore be relatively inexpensive.

Abstract: Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.

Abstract: Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.

Abstract: A computing chip can include one or more voltage regulators to decrease a standard voltage, such as twelve volts, to a relatively low operating voltage of its processing cores, typically around one volt. Because the power consumed by the cores can be substantial, such as three hundred watts or more, it is desirable to locate the voltage regulators as close as possible to the cores, to reduce the distances that relatively large currents have to travel in the chip circuitry. The voltage regulators can be embedded within the package, such as in a layered structure, in a layer that electrically connects to the cores. While the cores are typically manufactured using the smallest possible lithographic features, the voltage regulators are less demanding and can instead use relatively large lithographic features, which can be formed using relatively old technology, and can therefore be relatively inexpensive.

Abstract: Techniques are described for fabricating integrated circuit devices that span multiple reticle fields. Integrated circuits formed within separate reticle fields are placed into electrical contact with each other by overlapping reticle fields to form an overlapping conductive interconnect. This overlapping conductive interconnect electrically connects an interconnect layer of a first reticle field with an interconnect layer of a second, laterally adjacent reticle field. The overlapping conductive interconnection extends into a common scribe zone between adjacent reticle fields.

Abstract: Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.

Abstract: In some examples, a voltage protection apparatus includes a circuit to compare an input voltage of a processor to a threshold voltage, and to provide a throttle signal to the processor if the input voltage of the processor droops below the threshold voltage. The processor input voltage can then be set to a lower voltage and the processor power can thus be lowered.

Abstract: Embodiments are generally directed to integrated passive devices on chip. An embodiment of a device includes a semiconductor die; a semiconductor die package, a first side of the package being coupled with the semiconductor die; and one or more separate dies to provide passive components for operation of the semiconductor die, wherein the passive components for operation of the semiconductor die includes inductors.

Abstract: A mesh interconnect interface includes a dielectric slice; first micro-bumps aligned along a longitudinal axis and positioned closest to a driver bank, which is to be coupled to a first mesh stop of a first chiplet; second micro-bumps similarly aligned and positioned farthest from the first driver bank; third micro-bumps similarly aligned and positioned closest to a second driver bank, which is to be coupled to a second mesh stop of a second chiplet; fourth micro-bumps similarly aligned and positioned farthest from the second driver bank, wherein the longitudinal axis is orthogonal to a gap between the chiplets. The groups of micro-bumps are disposed on the slice. A first group of wires are embedded in the slice to couple the first and second micro-bumps. A second group of wires are interleaved with the first group of wires and embedded in the slice to couple the second and third micro-bumps.

Abstract: Embodiments are generally directed to hybrid magnetic material structures for electronic devices and circuits. An embodiment of an inductor includes a first layer of magnetic film material applied on a substrate, one or more conductors placed on the first layer of magnetic film material, and a second layer of magnetic particles, wherein the magnetic particles are suspended in an insulating medium.

Abstract: Stacked semiconductor die architectures having thermal spreaders disposed between stacked semiconductor dies and techniques of forming such architectures are described. The stacked semiconductor die architectures may be included in or used to form semiconductor packages. A stacked semiconductor die architecture can include: (i) a base die; (ii) a plurality of stacked semiconductor dies arranged on the base die; and (iii) at least one thermal spreader disposed in one or more gaps between the plurality of stacked semiconductor dies or in one or more areas on the base die that are adjacent to the plurality of stacked semiconductor dies. The thermal spreaders can assist with thermal management of the dies, which can assist with improving the power density of the stacked semiconductor die architecture. At least one other stacked semiconductor die architecture s also described.

Abstract: A locking position stud fastener is configured to position, lock, and securely hold a lamp assembly to a vehicle body. A method for installing a lamp assembly on to a vehicle body having at least one opening for receiving a fastener includes the steps of securing a first end of a stud to the lamp assembly, rotating the stud about its axis, passing the stud through the vehicle body opening, and then locking and securing the stud in the vehicle body.

Abstract: Stacked semiconductor die architectures having thermal spreaders disposed between stacked semiconductor dies and techniques of forming such architectures are described. The stacked semiconductor die architectures may be included in or used to form semiconductor packages. A stacked semiconductor die architecture can include: (i) a base die; (ii) a plurality of stacked semiconductor dies arranged on the base die; and (iii) at least one thermal spreader disposed in one or more gaps between the plurality of stacked semiconductor dies or in one or more areas on the base die that are adjacent to the plurality of stacked semiconductor dies. The thermal spreaders can assist with thermal management of the dies, which can assist with improving the power density of the stacked semiconductor die architecture. At least one other stacked semiconductor die architecture s also described.

Abstract: Embodiments are generally directed to integrated passive devices on chip. An embodiment of a device includes a semiconductor die; a semiconductor die package, a first side of the package being coupled with the semiconductor die; and one or more separate dies to provide passive components for operation of the semiconductor die, wherein the passive components for operation of the semiconductor die includes inductors.

Abstract: Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.

Abstract: Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.

Abstract: Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.

Abstract: Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.

Abstract: Embodiments are generally directed to hybrid magnetic material structures for electronic devices and circuits. An embodiment of an inductor includes a first layer of magnetic film material applied on a substrate, one or more conductors placed on the first layer of magnetic film material, and a second layer of magnetic particles, wherein the magnetic particles are suspended in an insulating medium.