Abstract: Embodiments of the present disclosure provide an integrated circuit (IC) structure, which can include: a semiconductor fin; a gate dielectric positioned above a first region of the semiconductor fin; a spacer positioned above a second region of the semiconductor fin and adjacent to the gate dielectric; and a source/drain region contacting a third region of the semiconductor fin; wherein the first region of the semiconductor fin includes substantially vertical sidewalls, and the third region of the semiconductor fin includes sloped sidewalls.

Abstract: Disclosed are field effect transistor (FET) formation methods using a final gate cut process and the resulting structures. One method forms an elongated gate across first and second semiconductor bodies for first and second FETs, respectively. An opening is formed in a portion of the elongated gate between the semiconductor bodies, cutting at least the gate conductor layer. The opening is filled with an isolation layer, thereby forming an isolation region that segments the elongated gate into first and second gates for the first and second FETs, respectively. Another method forms at least three gates across an elongated semiconductor body. An isolation region is formed that extends, not only through a portion of a center one of the gates, but also through a corresponding portion of the elongated semiconductor body adjacent to that gate, thereby segmenting the elongated semiconductor body into discrete semiconductor bodies for first and second FETs.

Abstract: Various embodiments provide systems, computer program products and computer implemented methods. In some embodiments, a system includes a computer-implemented method of determining a laterally diffuse dopant profile in semiconductor structures by providing first and second semiconductor structures having plurality of gate array structures in a silicided region separated from each other by a first distance and second distance. A potential difference is applied across the plurality of gate array structures and resistances are determined. A linear-regression fit is performed on measured resistance versus the first distance and the second distance with an extrapolated x equals 0 and a y-intercept to determine a laterally diffused dopant-profile under the plurality of gate array structures based on a semiconductor device model.

Abstract: A method of single-fin removal for quadruple density fins. A first double density pattern of first sidewall spacers is produced on a semiconductor substrate from first mandrels formed by a first mask using a minimum pitch. A second double density pattern of second sidewall spacers is produced on a layer disposed above the first double density pattern from second mandrels formed by a second mask with a the minimum pitch that is shifted relative to the first mask. A single sidewall spacer is removed from either the first or second double density pattern of first and second sidewall spacers. Sidewall image transfer processes allow the formation of quadruple density fins from which but a single fin is removed.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a symmetric tunnel field effect transistor and methods of manufacture. The structure includes a gate structure including a source region and a drain region both of which comprise a doped VO2 region.

Abstract: Disclosed are isolation techniques for bulk FinFETs. A semiconductor device includes a semiconductor substrate with a fin structure on the semiconductor substrate. The fin structure is perpendicular to the semiconductor substrate and has an upper portion and a lower portion. Source and drain regions are adjacent to the fin structure. A gate structure surrounds the upper portion of the fin structure. A well contact point is provided in the semiconductor substrate. The lower portion of the fin structure includes a sub-fin between the region surrounded by the gate structure and the semiconductor substrate. The sub-fin directly contacts the semiconductor substrate. The upper portion of the fin structure and an upper portion of the sub-fin are undoped. A lower portion of the sub-fin may be doped. Electrical potential applied from the well contact point to the lower portion of the sub-fin reduces leakage currents from the upper portion of the fin structure.

Abstract: The integrated circuit described herein includes: a first resistor having a first trench in a dielectric layer, the first trench having a first width; a second resistor having a second trench in the dielectric layer, the second trench having a second width not equal to the first width; a trench in a dielectric layer; a first conductive layer having a first TCR and coating at least a portion of the first trench and the second trench; and a second conductive layer having a second TCR and coating at least a portion of the first conductive layer in each of the first trench and the second trench, wherein the second TCR is not equal to the first TCR, and wherein the TCR of the IC is selected based on a dimension of the trench, a thickness of the first conductive layer, and a thickness of the second conductive layer.

Abstract: Disclosed are non-planar capacitors with finely tuned capacitances and methods of forming them. The capacitors each incorporate one or more semiconductor bodies and one or more gate stacks traversing the one or more semiconductor bodies. At least one first semiconductor body is etched so that it is shorter in length than the others, which are incorporated into other non-planar devices and/or into the same non-planar capacitor. Additionally, at least one gate stack can be formed so that it traverses a first portion and, particularly, an end portion of the shortened semiconductor body and further so that it extends laterally some distance beyond that first portion. In such capacitors, the length of the first portion of the shorted semiconductor body, which corresponds to a capacitor conductor and which is traversed by the gate stack, which corresponds to a capacitor dielectric and another capacitor conductor, is predetermined to achieve a desired capacitance.

Abstract: Disclosed are field effect transistor (FET) formation methods using a final gate cut process and the resulting structures. One method forms an elongated gate across first and second semiconductor bodies for first and second FETs, respectively. An opening is formed in a portion of the elongated gate between the semiconductor bodies, cutting at least the gate conductor layer. The opening is filled with an isolation layer, thereby forming an isolation region that segments the elongated gate into first and second gates for the first and second FETs, respectively. Another method forms at least three gates across an elongated semiconductor body. An isolation region is formed that extends, not only through a portion of a center one of the gates, but also through a corresponding portion of the elongated semiconductor body adjacent to that gate, thereby segmenting the elongated semiconductor body into discrete semiconductor bodies for first and second FETs.

Abstract: A semiconductor device and method of manufacturing is disclosed which has a tensile and/or compressive strain applied thereto. The method includes forming at least one trench in a material; and filling the at least one trench by an oxidation process thereby forming a strain concentration in a channel of a device. The structure includes a gate structure having a channel and a first oxidized trench on a first of the channel, respectively. The first oxidized trench creates a strain component in the channel to increase device performance.

Abstract: Systems and methods of forming semiconductor devices. A trench capacitor comprising deep trenches is formed in an n+ type substrate. The deep trenches have a lower portion partially filled with a trench conductor surrounded by a storage dielectric. A polysilicon growth is formed in an upper portion of the deep trenches. The semiconductor device includes a single-crystal semiconductor having an angled seam separating a portion of the polysilicon growth from an exposed edge of the deep trenches. A word-line is wrapped around the single-crystal semiconductor. A bit-line overlays the single-crystal semiconductor.

Abstract: Vertical field effect transistors (FETs) with minimum pitch and methods of manufacture are disclosed. The structure includes at least one vertical fin structure and gate material contacting with the at least one vertical fin structure. The structure further includes metal material in electrical contact with the ends of the at least one vertical fin.

Abstract: Vertical field effect transistors (FETs) with minimum pitch and methods of manufacture are disclosed. The structure includes at least one vertical fin structure and gate material contacting with the at least one vertical fin structure. The structure further includes metal material in electrical contact with the ends of the at least one vertical fin.

Abstract: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a high-leakage dielectric formed over an active region of a FET and a low-leakage dielectric formed on the active region and adjacent the high-leakage dielectric. The low-leakage dielectric has a lower leakage than the high-leakage dielectric. Also provided is a structure and method of fabricating the structure.

Abstract: Embodiments of the present disclosure provide an integrated circuit (IC) structure, which can include: a doped semiconductor layer having a substantially uniform doping profile; a first gate structure positioned on the doped semiconductor layer; and a second gate structure positioned on the doped semiconductor layer, the second gate structure including a metal-insulator transition material and a gate dielectric layer separating the metal-insulator transition material from the doped semiconductor layer.

Abstract: Some embodiments of the present invention may include one, or more, of the following features, characteristics or advantages: (i) latch device including multiple Ecrit material regions all electrically connected to a common terminal (sometimes structured and shaped in the form of a storage plate conductor); (ii) bi-stable three-terminal latch device using two Ecrit property regions; (iii) three-terminal, two-Ecrit-region latch device where, for each Ecrit region, (Vdd?Vss) divided by (region thickness, dn) is greater than the region's Ecrit value; or (iv) use of multiple Ecrit material region latch devices to provide data storage instrumentality in a static memory device.

Abstract: Embodiments of the present disclosure provide an integrated circuit (IC) structure, which can include: a doped semiconductor layer having a substantially uniform doping profile; a first gate structure positioned on the doped semiconductor layer; and a second gate structure positioned on the doped semiconductor layer, the second gate structure including a metal-insulator transition material and a gate dielectric layer separating the metal-insulator transition material from the doped semiconductor layer.

Abstract: A semiconductor memory device including a channel region and a ferromagnetic gate is provided. The channel region can be formed within a semiconductor nanowire. The ferromagnetic gate is programmed with a selected orientation of magnetization by the electrical current that passes through the channel region in one direction or another. The orientation of the magnetization in the ferromagnetic gate can be detected by changes in the threshold voltage of a field effect transistor employing the ferromagnetic gate as a gate electrode, or can be detected by the resistance of the channel region that changes with the orientation of the magnetization in a two terminal device.

Abstract: Disclosed are semiconductor structures comprising a field effect transistor (FET) having a low-resistance source/drain contact and, optionally, low gate-to-source/drain contact capacitance. The structures comprise a semiconductor body and, contained therein, first and second source/drain regions and a channel region. A first gate is adjacent to the semiconductor body at the channel region and a second, non-functioning, gate is adjacent to the semiconductor body such that the second source/drain region is between the first and second gates. First and second source/drain contacts are on the first and source/drain regions, respectively. The second source/drain contact is wider than the first and, thus, has a lower resistance. Additionally, spacing of the first and second source/drain contacts relative to the first gate can be such that the first gate-to-second source/drain contact capacitance is equal to or less than the first gate-to-first source/drain contact capacitance.

Abstract: Structures and methods of manufacturing a fin-type PIN diode array include forming a plurality of first charge-type doped silicon fins disposed in parallel on a planar substrate in a first direction, forming undoped epitaxial growths of silicon at intervals along a length of each silicon fin, where each epitaxial growth includes a depleted intrinsic region, and forming a plurality of second charge-type doped polysilicon fins disposed in parallel and disposed perpendicularly to the first direction. The polysilicon fins are formed to contact, at intervals along a length of each polysilicon fin, an uppermost surface of one of the undoped epitaxial growths of silicon, to form a PIN diode at each intersection of each of the first charge-type doped silicon fins and the second charge-type doped polysilicon fins.