Patents by Inventor Edward Roberts

Edward Roberts has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11928471
    Abstract: Embodiments for a metadata predictor. An index pipeline generates indices in an index buffer in which the indices are used for reading out a memory device. A prediction cache is populated with metadata of instructions read from the memory device. A prediction pipeline generates a prediction using the metadata of the instructions from the prediction cache, the populating of the prediction cache with the metadata of the instructions being performed asynchronously to the operating of the prediction pipeline.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: March 12, 2024
    Assignee: International Business Machines Corporation
    Inventors: Edward Thomas Malley, Adam Benjamin Collura, Brian Robert Prasky, James Bonanno, Dominic Ditomaso
  • Publication number: 20240073023
    Abstract: Various aspects of the subject technology relate to systems, methods, and machine-readable media for connecting to an independent software vendor (ISV). The method includes receiving, at an integrated platform, a request to initiate a data connection with the ISV. The request may include a web address of the ISV. The method also includes associating, through the integrated platform, the data connection with a unique identifier. The method also includes issuing an authorization code based on authentication of an authorization request for the data connection. The method also includes exchanging, with a connector service, the authorization code for tokens utilized for establishing the data connection with the ISV. The method also includes receiving access to the ISV through the integrated platform.
    Type: Application
    Filed: November 8, 2023
    Publication date: February 29, 2024
    Inventors: Edward Robert Sutter, Ian Matthew Nicholson, Thomas Anthony Schoendorfer
  • Publication number: 20240072131
    Abstract: Strategic placement and patterning of electrodes, vias, and metal runners can significantly reduce strain in a power semiconductor die. By modifying the path defining electrodes, vias, and metal runners, as well as patterning the material layers thereof, strain can be better managed to increase reliability of a power semiconductor die.
    Type: Application
    Filed: November 8, 2023
    Publication date: February 29, 2024
    Inventors: Daniel Jenner Lichtenwalner, Edward Robert Van Brunt, Thomas E. Harrington, III, Shadi Sabri, Brett Hull, Brice McPherson, Joe W. McPherson
  • Patent number: 11897873
    Abstract: Compounds are provided that antagonize the kappa-opioid receptor (KOR) and products containing such compounds, as well as to methods of their use and synthesis. Such compounds have the structure of Formula (I), or a pharmaceutically acceptable isomer, racemate, hydrate, solvate, isotope or salt thereof: wherein X, Y, R1, R2, R4, R5, R6, R7, R8 and R11 are as defined herein.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: February 13, 2024
    Assignees: BLACKTHORN THERAPEUTICS, INC., THE SCRIPPS RESEARCH INSTITUTE
    Inventors: Edward Roberts, Miguel A. Guerrero, Mariangela Urbano, Hugh Rosen, Robert M. Jones, Candace Mae Laxamana, Xianrui Zhao, Eric Douglas Turtle
  • Publication number: 20240037613
    Abstract: A system includes a memory comprising a first preference profile and a second preference profile, a correlation module configured to determine a correlation value between the first preference profile and the second preference profile, and a module configured to take an action as a function of the correlation value. The action is changing a physical configuration of signage from a first physical configuration to a second physical configuration.
    Type: Application
    Filed: October 9, 2023
    Publication date: February 1, 2024
    Inventor: Mark Edward Roberts
  • Publication number: 20240012984
    Abstract: A system for creating an output comprises a processing unit, a user input module operably connected to the processing unit, and a display operably connected to the processing unit. The processing unit provides on the display: a grid image comprising multiple cells, each cell representing a duration of time; and a selection area comprising multiple select icons, each select icon representing a source data file. The processing unit is configured such that a user can create a grid layout representing the correlation between individual selected source data files and one, two, or more of the multiple cells. The processing unit produces the output based on the correlation.
    Type: Application
    Filed: February 1, 2023
    Publication date: January 11, 2024
    Inventors: Carmine Silano, Edward Roberts, R. Maxwell Flaherty, J. Christopher Flaherty
  • Patent number: 11869948
    Abstract: Strategic placement and patterning of electrodes, vias, and metal runners can significantly reduce strain in a power semiconductor die. By modifying the path defining electrodes, vias, and metal runners, as well as patterning the material layers thereof, strain can be better managed to increase reliability of a power semiconductor die.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: January 9, 2024
    Assignee: Wolfspeed, Inc.
    Inventors: Daniel Jenner Lichtenwalner, Edward Robert Van Brunt, Thomas E. Harrington, III, Shadi Sabri, Brett Hull, Brice McPherson, Joe W. McPherson
  • Patent number: 11863673
    Abstract: Various aspects of the subject technology relate to systems, methods, and machine-readable media for connecting to an independent software vendor (ISV). The method includes receiving, at an integrated platform, a request to initiate a data connection with the ISV. The request may include a web address of the ISV. The method also includes associating, through the integrated platform, the data connection with a unique identifier. The method also includes issuing an authorization code based on authentication of an authorization request for the data connection. The method also includes exchanging, with a connector service, the authorization code for tokens utilized for establishing the data connection with the ISV. The method also includes receiving access to the ISV through the integrated platform.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: January 2, 2024
    Assignee: AppDirect, Inc.
    Inventors: Edward Robert Sutter, Ian Matthew Nicholson, Thomas Anthony Schoendorfer
  • Publication number: 20230420577
    Abstract: A semiconductor device includes a drift region, an active region in the drift region, and an edge termination region in the drift region adjacent to the active region. The edge termination region includes one or more guard rings in the drift region. The drift region has a first conductivity type and the one or more guard rings have a second conductivity type. The edge termination region may also include a passivation layer that is disposed on the one or more guard rings and on the drift region in the edge termination region. The passivation layer has a first thickness over each guard ring and a second thickness over the drift region, where the first thickness is greater than the second thickness. Alternatively, the edge termination region may also include a passivation layer that is only disposed on the one or more guard rings in the edge termination region.
    Type: Application
    Filed: June 24, 2022
    Publication date: December 28, 2023
    Inventors: In-Hwan Ji, Edward Robert Van Brunt, Woongsun Kim
  • Publication number: 20230420575
    Abstract: A method of forming a buried implanted region in a silicon carbide semiconductor layer includes implanting first dopant ions into the silicon carbide semiconductor layer at a first dose and first implant energy to form a first channelized doping profile having a first de-channeled peak at a first depth in the silicon carbide semiconductor layer and a first channeled peak at a second depth that is greater than the first depth. Second dopant ions are implanted into the silicon carbide semiconductor layer at a second dose and second implant energy to form a second channelized doping profile. The second channelized doping profile has a second channeled peak at a third depth in the silicon carbide semiconductor layer that is between the first depth and the second depth. The first channelized doping profile and the second channelized doping profile form a combined doping profile that defines the buried implanted region.
    Type: Application
    Filed: June 24, 2022
    Publication date: December 28, 2023
    Inventors: Rahul R. Potera, Steven Rogers, Edward Robert Van Brunt
  • Patent number: 11838383
    Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may determine, by an edge enabler client of the UE, to trigger generation of a shadow application context to support an application that is associated with an application context and that is served by an edge network device. The UE may determine, by the edge enabler client, to transfer support of the application from the application context to the shadow application context, and transfer, by the edge enabler client, support of the application from the application context to the shadow application context. In some aspects, an application context may be transferred between a UE and an edge network directly, without the shadow application context. Numerous other aspects are provided.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: December 5, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Edward Robert Hall, Alan Soloway, Thomas Stockhammer, Imed Bouazizi
  • Publication number: 20230389060
    Abstract: Embodiments include methods performed by a processor of a mobile device for allocating resources to a plurality of mobile devices in communication with an Edge network. The processor may receive from the plurality of mobile devices one or more capabilities of each mobile device related to a computing task in which the plurality of mobile devices are participating. The processor may determine a fairness result for the plurality of computing devices based on the one or more capabilities of each mobile device and the computing task. The processor may allocate resources to each of the plurality of mobile devices based on the determined fairness result.
    Type: Application
    Filed: June 11, 2023
    Publication date: November 30, 2023
    Inventors: Alan Soloway, Edward Robert Hall, Thomas Stockhammer
  • Patent number: 11824830
    Abstract: A network interface device having a hardware module comprising a plurality of processing units. Each of the plurality of processing units is associated with its own at least one predefined operation. At a compile time, the hardware module is configured by arranging at least some of the plurality of processing units to perform their respective at least one operation with respect to a data packet in a certain order so as to perform a function with respect to that data packet. A compiler is provide to assign different processing stages to each processing unit. A controller is provided to switch between different processing circuitry on the fly so that one processing circuitry may be used whilst another is being compiled.
    Type: Grant
    Filed: April 30, 2021
    Date of Patent: November 21, 2023
    Assignee: Xilinx, Inc.
    Inventors: Steven Leslie Pope, Neil Turton, David James Riddoch, Dmitri Kitariev, Ripduman Sohan, Derek Edward Roberts
  • Publication number: 20230362129
    Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may store, in a domain name system (DNS) cache, DNS information associated with an edge application server at which an application context, associated with an application client resident on the UE, is located. The UE may receive a first message associated with a handover of the UE or a second message associated with a transfer of the application context. The UE may modify the DNS cache, by updating the DNS information or flushing the DNS information, based at least in part on receiving the first message or the second message. Numerous other aspects are provided.
    Type: Application
    Filed: July 26, 2021
    Publication date: November 9, 2023
    Inventors: Edward Robert HALL, Dario Serafino TONESI, Sunghoon KIM, Haris ZISIMOPOULOS
  • Publication number: 20230361212
    Abstract: A semiconductor device includes a device region and an on-chip sensor region, such as an on-chip current sensor region. The semiconductor device further includes a transition region formed between the device region and the sensor region. A gate contact extends across the transition region. A conductive segment may be formed on the gate contact in the transition region to reduce a resistivity of the material used to form the gate contact. Additionally or alternatively, an isolation region may be formed under the gate contact between a first isolated well region in the device region and a second isolated well region in the sensor region. The isolation region isolates the first isolated well region from the second isolated well region to prevent current in the device region from propagating into the sensor region.
    Type: Application
    Filed: May 4, 2022
    Publication date: November 9, 2023
    Inventors: Madankumar Sampath, Sei-Hyung Ryu, Edward Robert Van Brunt
  • Patent number: 11791378
    Abstract: Semiconductor devices include a silicon carbide drift region having an upper portion and a lower portion. A first contact is on the upper portion of the drift region and a second contact is on the lower portion of the drift region. The drift region includes a superjunction structure that includes a p-n junction that is formed at an angle of between 10° and 30° from a plane that is normal to a top surface of the drift region. The p-n junction extends within +/?1.5° of a crystallographic axis of the silicon carbide material forming the drift region.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: October 17, 2023
    Assignee: Wolfspeed, Inc.
    Inventors: Edward Robert Van Brunt, Alexander V. Suvorov, Vipindas Pala, Daniel J. Lichtenwalner, Qingchun Zhang
  • Publication number: 20230327026
    Abstract: A power transistor device includes a drift layer having a first conductivity type and a mesa on the drift layer. The mesa includes a channel region on the drift layer, a source layer on the channel region and a gate region in the mesa adjacent the channel region. The channel region and the source layer have the first conductivity type, and the gate region has a second conductivity type opposite the first conductivity type. The channel region includes a deep conduction region and a shallow conduction region between the deep conduction region and the gate region. The deep conduction region has a first doping concentration, and the shallow conduction region has a second doping concentration that is greater than the first doping concentration.
    Type: Application
    Filed: March 25, 2022
    Publication date: October 12, 2023
    Inventors: Rahul R. Potera, Thomas E. Harrington, III, Edward Robert Van Brunt, Madankumar Sampath
  • Patent number: 11743808
    Abstract: Systems and methods for user equipment (UE) triggered edge computing application context relocation in an edge computing application architecture are described. For example, in facilitating relocation of an application context from a source edge application server (S-EAS) served by a source edge enabler server (S-EES) to a target EAS (T-EAS) served by a target EES (T-EES), S-EES centric and/or T-EES centric UE triggered application context relocation procedures may be implemented. In accordance with S-EES centric and/or T-EES centric UE triggered application context relocation procedures of some examples, a UE may take primary responsibility with respect to the application context transfer. Other aspects and features are also claimed and described.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: August 29, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Sunghoon Kim, Edward Robert Hall, Alan Soloway, Tom Chin
  • Patent number: D1009495
    Type: Grant
    Filed: October 13, 2021
    Date of Patent: January 2, 2024
    Assignee: BETA AIR, LLC
    Inventor: Edward Robert Hall
  • Patent number: D1012179
    Type: Grant
    Filed: October 13, 2021
    Date of Patent: January 23, 2024
    Assignee: BETA AIR, LLC
    Inventor: Edward Robert Hall