Abstract: Contact structures for semiconductor devices are disclosed. Contact structures that include a metal layer and a substrate of a semiconductor device may be annealed to provide suitable contact resistance. Localized annealed regions may be formed in a pattern within the contact structure to provide a desired contact resistance while reducing exposure of other portions of the semiconductor device to anneal conditions. The annealed regions may be formed in patterns that reduce intersections between annealed regions and fracture planes of the substrate, thereby improving mechanical robustness of the semiconductor device. The patterns may include annealed regions formed in lines that are nonparallel with fracture planes of the substrate. The patterns may also include annealed regions formed in lines that are nonparallel with peripheral edges of the substrate.

Abstract: Methods, systems, and devices for wireless communications are described that provide for configuration of edge data networks based on current and projected future locations of a user equipment (UE). The UE may provide one or more expected future locations based on routing information of the UE, a polygon associated with one or more current or future UE locations, a waypoint set of the UE, and the like. Based on the provided one or more future locations, the edge data network may provide to the UE one or more edge data network configurations for different UE locations. As the UE moves to different locations, different edge data network configurations may be used, thereby enhancing efficiency of UE operation in the edge data network.

Abstract: A transistor semiconductor die includes a drift layer, a first dielectric layer, a first metallization layer, a second dielectric layer, a second metallization layer, a first plurality of electrodes, and a second plurality of electrodes. The first dielectric layer is over the drift layer. The first metallization layer is over the first dielectric layer such that at least a portion of the first metallization layer provides a first contact pad. The second dielectric layer is over the first metallization layer. The second metallization layer is over the second dielectric layer such that at least a portion of the second metallization layer provides a second contact pad and the second metallization layer at least partially overlaps the first metallization layer. The transistor semiconductor die is configured to selectively conduct current between the first contact pad and a third contact pad based on signals provided at the second contact pad.

Abstract: Apparatus for use in providing isolation, the apparatus including an isolation tent having a body including a roof member, at least one wall extending between a supporting surface and the roof member in use to thereby at least partially define an internal volume substantially isolated from a surrounding environment, a plurality of connectors coupled to the body, the plurality of connectors being adapted to physically attach the body to a frame and an electrical component electrically connected to at least one of the plurality of connectors to allow electrical signals to be transferred to or from the electrical component via the connector.

Abstract: An apparatus and method for synchronising advertisements published on a group communications network with advertisements in a broadcast, the apparatus comprising: a receiver for receiving broadcast data; a communications interface in communication with a group communications network; a broadcast data content extractor adapted to derive search terms and advert data from the received broadcast data, the advert data relating to an advert received in the broadcast data, wherein on receipt of a query by a user of the group communications network, the query comprising one or more of the search terms, the communications interface publishes a group communication comprising at least a portion of the advert data on the group communications network.

Abstract: Systems, methods and media for adaptive real time modeling and scoring are provided. In one example, a system for automatically generating predictive scoring models comprises a trigger component to determine, based on a threshold or trigger, such as a detection of new significant relationships, whether a predictive scoring model is ready for a refresh or regeneration. An automated modeling sufficiency checker receives and transforms user-selectable system input data. The user-selectable system input data may comprise at least one of email, display or social media traffic. An adaptive modeling engine operably connected to the trigger component and modeling sufficiency checker is configured to monitor and identify a change in the input data and, based on an identified change in the input data, automatically refresh or regenerate the scoring model for calculating new lead scores. A refreshed or regenerated predictive scoring model is output.

Abstract: Systems and methods for user equipment (UE) triggered edge computing application context relocation in an edge computing application architecture are described. For example, in facilitating relocation of an application context from a source edge application server (S-EAS) served by a source edge enabler server (S-EES) to a target EAS (T-EAS) served by a target EES (T-EES), S-EES centric and/or T-EES centric UE triggered application context relocation procedures may be implemented. In accordance with S-EES centric and/or T-EES centric UE triggered application context relocation procedures of some examples, a UE may take primary responsibility with respect to the application context transfer. Other aspects and features are also claimed and described.

Abstract: A semiconductor device includes a semiconductor layer structure that includes silicon carbide, a gate dielectric layer on the semiconductor layer structure, and a gate electrode on the gate dielectric layer opposite the semiconductor layer structure. In some embodiments, a periphery of a portion of the gate dielectric layer that underlies the gate electrode is thicker than a central portion of the gate dielectric layer, and a lower surface of the gate electrode has recessed outer edges such as rounded and/or beveled outer edges.

Abstract: A data processing system arranged for receiving over a network, according to a data transfer protocol, data directed to any of a plurality of destination identities, the data processing system comprising: data storage for storing data received over the network; and a first processing arrangement for performing processing in accordance with the data transfer protocol on received data in the data storage, for making the received data available to respective destination identities; and a response former arranged for: receiving a message requesting a response indicating the availability of received data to each of a group of destination identities; and forming such a response; wherein the system is arranged to, in dependence on receiving the said message.

Abstract: Contact structures for semiconductor devices are disclosed. Contact structures that include a metal layer and a substrate of a semiconductor device may be annealed to provide suitable contact resistance. Localized annealed regions may be formed in a pattern within the contact structure to provide a desired contact resistance while reducing exposure of other portions of the semiconductor device to anneal conditions. The annealed regions may be formed in patterns that reduce intersections between annealed regions and fracture planes of the substrate, thereby improving mechanical robustness of the semiconductor device. The patterns may include annealed regions formed in lines that are nonparallel with fracture planes of the substrate. The patterns may also include annealed regions formed in lines that are nonparallel with peripheral edges of the substrate.

Abstract: Semiconductor devices include a silicon carbide drift region having an upper portion and a lower portion. A first contact is on the upper portion of the drift region and a second contact is on the lower portion of the drift region. The drift region includes a superjunction structure that includes a p-n junction that is formed at an angle of between 10° and 30° from a plane that is normal to a top surface of the drift region. The p-n junction extends within +/?1.5° of a crystallographic axis of the silicon carbide material forming the drift region.

Abstract: A computer-implemented method of facilitating electrocardiogram (“ECG”) analysis involves receiving one or more sensed ECG traces for a patient, each of the sensed ECG traces representing sensed patient heart activity over a sensed time period, and, for each of the one or more sensed ECG traces: identifying a plurality of corresponding sensed ECG trace segments, each of the sensed ECG trace segments representing sensed patient heart activity for the patient over a segment of the sensed time period, and determining a representative ECG trace based on at least one of the identified corresponding sensed ECG trace segments. The method involves causing at least one neural network classifier to be applied to the one or more determined representative ECG traces to determine one or more diagnostically relevant scores related to at least one diagnosis of the patient. Other methods, systems, and computer readable media are disclosed.

Abstract: A system for creating an output comprises a processing unit, a user input module operably connected to the processing unit, and a display operably connected to the processing unit. The processing unit provides on the display: a grid image comprising multiple cells, each cell representing a duration of time; and a selection area comprising multiple select icons, each select icon representing a source data file. The processing unit is configured such that a user can create a grid layout representing the correlation between individual selected source data files and one, two, or more of the multiple cells. The processing unit produces the output based on the correlation.

Abstract: Power switching devices include a semiconductor layer structure comprising an active region and an inactive region, the active region comprising a plurality of unit cells and the inactive region comprising a gate pad on the semiconductor layer structure and a gate bond pad on and electrically connected to the gate pad, an isolation layer between the gate pad and the gate bond pad, and a barrier layer between the gate pad and the isolation layer.

Abstract: A transistor semiconductor die includes a drift layer, a first dielectric layer, a first metallization layer, a second dielectric layer, a second metallization layer, a first plurality of electrodes, and a second plurality of electrodes. The first dielectric layer is over the drift layer. The first metallization layer is over the first dielectric layer such that at least a portion of the first metallization layer provides a first contact pad. The second dielectric layer is over the first metallization layer. The second metallization layer is over the second dielectric layer such that at least a portion of the second metallization layer provides a second contact pad and the second metallization layer at least partially overlaps the first metallization layer. The transistor semiconductor die is configured to selectively conduct current between the first contact pad and a third contact pad based on signals provided at the second contact pad.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may determine, by an edge enabler client of the UE, to trigger generation of a shadow application context to support an application that is associated with an application context and that is served by an edge network device. The UE may determine, by the edge enabler client, to transfer support of the application from the application context to the shadow application context, and transfer, by the edge enabler client, support of the application from the application context to the shadow application context. In some aspects, an application context may be transferred between a UE and an edge network directly, without the shadow application context. Numerous other aspects are provided.

Abstract: A semiconductor device includes a semiconductor layer structure that includes silicon carbide, a gate dielectric layer on the semiconductor layer structure, and a gate electrode on the gate dielectric layer opposite the semiconductor layer structure. In some embodiments, a periphery of a portion of the gate dielectric layer that underlies the gate electrode is thicker than a central portion of the gate dielectric layer, and a lower surface of the gate electrode has recessed outer edges such as rounded and/or beveled outer edges.

Abstract: A computer-implemented method of facilitating electrocardiogram (“ECG”) analysis involves receiving one or more sensed ECG traces for a patient, each of the sensed ECG traces representing sensed patient heart activity over a sensed time period, and, for each of the one or more sensed ECG traces: identifying a plurality of corresponding sensed ECG trace segments, each of the sensed ECG trace segments representing sensed patient heart activity for the patient over a segment of the sensed time period, and determining a representative ECG trace based on at least one of the identified corresponding sensed ECG trace segments. The method involves causing at least one neural network classifier to be applied to the one or more determined representative ECG traces to determine one or more diagnostically relevant scores related to at least one diagnosis of the patient. Other methods, systems, and computer readable media are disclosed.

Abstract: Compounds are provided that antagonize the kappa-opioid receptor (KOR) and products containing such compounds, as well as to methods of their use and synthesis. Such compounds have the structure of Formula (I), or a pharmaceutically acceptable isomer, racemate, hydrate, solvate, isotope or salt thereof: wherein X, Y, R1, R2, R4, R5 R6, R7, R8 and R11 are as defined herein.

Abstract: Wafer images and related alignment methods for crystalline wafers are disclosed. Certain aspects relate to accessing and aligning images of a same or similar crystalline wafer captured from different imaging sources. Alignment may include determining spatial differences between shared crystalline features in various wafer images of the same or similar crystalline wafer and transforming at least one of the images according to the determined spatial differences. With sufficient alignment, information may be associated and/or transferred between the various images, thereby providing the capability of forming a combined wafer image and sub-images thereof with high resolution and spatial coordination between different image sources. Certain aspects relate to development of nondestructive, high fidelity defect characterization and/or dislocation counting methods in crystalline materials based on modern deep convolutional neural networks (DCNN).