Abstract: A display device and modulation scheme for applying image data to an imager is disclosed. The display may use a modulation scheme wherein spacing of row write actions on the rows creates gray scale modulation, wherein one row spacing between sequential row write actions is at a first distance while another row spacing between sequential row write actions is at a distance greater than said first distance. The modulation scheme may create a series of write pointers that create a corresponding series of write planes. In some embodiments, modulation efficiency is increased allowing the use of lower frequency imaging circuits to achieve the same display image.

Abstract: A method of organizing and ordering pulse width modulation image data is disclosed, so that it may be displayed on the pixels of a scrolling color display. The method includes a method of formatting received image data into a different form suitable for driving a pulse width modulated display and a method of distributing image data across a series of different image modulation segments to minimize flicker and gray scale errors. The method includes means for reducing lateral field effects between adjacent pixels in different data states.

Abstract: The present application provides a method of pulse width modulating a spatial light modulator. The method comprises determining a modulation sequence and applying said modulation sequence to said spatial light modulator in a time order method. Said modulation sequence comprises a plurality of minor modulation segments. Each minor modulation segment comprises an “always on” modulation segment in an “always on” state. Said plurality of minor modulation segments are temporally spaced such that said “always on” modulation segments are spaced at predetermined intervals. Each minor modulation segment comprises at least one thermometer bit.

Abstract: A micro-LED display device and modulation scheme for applying image data to an imager. The micro-LED display, including a plurality of micro-LED pixels disposed in rows and columns array, may use a modulation scheme. The method includes using row write actions to write data to said rows of micro-LED pixels; and using spacing of row write actions to create grey scale modulation, wherein one spacing between sequential row write actions is at a first distance while another spacing between sequential row write actions is at a second distance greater than said first distance.

Abstract: A method of organizing and ordering pulse width modulation image data is disclosed, so that it may be displayed on the pixels of a scrolling color display. The method includes a method of formatting received image data into a different form suitable for driving a pulse width modulated display and a method of distributing image data across a series of different image modulation segments to minimize flicker and gray scale errors. The method includes means for reducing lateral field effects between adjacent pixels in different data states.

Abstract: A display device and modulation scheme for applying image data to an imager is disclosed. The display may use a modulation scheme wherein spacing of row write actions on the rows creates gray scale modulation, wherein one row spacing between sequential row write actions is at a first distance while another row spacing between sequential row write actions is at a distance greater than said first distance. The modulation scheme may create a series of write pointers that create a corresponding series of write planes. In some embodiments, modulation efficiency is increased allowing the use of lower frequency imaging circuits to achieve the same display image.

Abstract: A display system which includes a display controller, a display unit, and a light source is disclosed. The display controller includes a processor unit, a memory device, a voltage source and, optionally, a light source control unit. The display unit includes an array of pixel cells and circuitry to receive logic and control voltages and data and operate the display, a transparent counter electrode, and a liquid crystal layer disposed between the two alignment layers. The pixel cell includes a storage element, a DC balance control switch, a pixel voltage override circuit, an inverter able to select between two voltages available to it, and a pixel electrode/mirror. In different modes of operation the pixel mirror voltage may be determined by the storage element or by the pixel voltage override circuit. The display system may display images in one period and reset to a fixed state in another period.

Abstract: A display device and modulation scheme for applying image data to an imager. The display may use a modulation scheme wherein spacing of row write actions on the rows creates gray scale modulation, wherein one row spacing between sequential row write actions is at a first distance while another row spacing between sequential row write actions is at a distance greater than said first distance. The modulation scheme may create a series of write pointers that create a corresponding series of write planes. In some embodiments, modulation efficiency is increased allowing the use of lower frequency imaging circuits to achieve the same display image.

Abstract: A multiplexed pixel display includes a plurality of pixel electrodes, a plurality of storage elements, a first voltage supply terminal, a second voltage supply terminal, a common electrode, and a plurality of multiplexers each selectively coupling an associated one of the pixel electrodes with one of the first voltage supply terminal and the second voltage supply terminal responsive to a value of a data bit stored in an associated one of said storage elements. A controller is configured to sequentially write each bit of multi-bit data words to the storage elements, and assert, while each bit is stored in the storage elements, a first predetermined voltage on the first voltage supply terminal, a second predetermined voltage on the second voltage supply terminal, and a third predetermined voltage on the common electrode, for a time dependent on the significance of the stored bit. Various alternate controllers facilitate the use of additional driving schemes.

Abstract: Methods, apparatus, and systems for generating drive sequences for pulse width modulated displays are described. A pulse width modulated signal that includes a drive sequence of temporal segments that are activated and deactivated to produce a desired gray scale. The temporal segments can be non-binary, non-equally weighted. The drive sequence can also include at least two of the temporal segments are least significant bit segments and the other segments are higher order segments.

Abstract: Methods, apparatus, and systems for generating drive sequences for pulse width modulated displays are described. A pulse width modulated signal that includes a drive sequence of temporal segments that are activated and deactivated to produce a desired gray scale. The temporal segments can be non-binary, non-equally weighted. The drive sequence can also include at least two of the temporal segments are least significant bit segments and the other segments are higher order segments.

Abstract: A display system which includes a display controller, a display unit, and a light source is disclosed. The display controller includes a processor unit, a memory device, a voltage source and, optionally, a light source control unit. The display unit includes an array of pixel cells and circuitry to receive logic and control voltages and data and operate the display, a transparent counter electrode, and a liquid crystal layer disposed between the two alignment layers. The pixel cell includes a storage element, a DC balance control switch, a pixel voltage override circuit, an inverter able to select between two voltages available to it, and a pixel electrode/mirror. In different modes of operation the pixel mirror voltage may be determined by the storage element or by the pixel voltage override circuit. The display system may display images in one period and reset to a fixed state in another period.

Abstract: Methods, apparatus, and systems for generating drive sequences for pulse width modulated displays are described. A pulse width modulated signal that includes a drive sequence of temporal segments that are activated and deactivated to produce a desired gray scale. The temporal segments can be non-binary, non-equally weighted. The drive sequence can also include at least two of the temporal segments are least significant bit segments and the other segments are higher order segments.

Abstract: A simplified pixel display includes a plurality of pixel electrodes, a plurality of storage elements, a single arbitrary voltage supply terminal, a second voltage supply terminal which may be either of the rail voltages of the display, a common electrode, and a plurality of externally controlled switches each selectively coupling an associated one of the pixel electrodes with one of the arbitrary voltage supply terminal and the second voltage supply terminal responsive to a value of a data bit stored in an associated one of said storage elements and to the state of the external control signal supplied to the switch.

Abstract: Methods, apparatus, and pulse width modulating a display include receiving image data and generating pulse data to be written to rows of pixels in a display. The data include a pulse width modulated drive sequence that writes data to selected rows on a first phase of a clock and terminates a write operation on a different row on a second phase of the clock.

Abstract: The present invention discloses a pixel display configuration by providing a voltage controller in each pixel control circuit for controlling the voltage inputted to the pixel electrodes. The controller includes a function of multiplexing the voltage input to the pixel electrodes and also a bit buffering and decoupling function to decouple and flexible change the input voltage level to the pixel electrodes. The rate of DC balancing can be increased to one KHz and higher to mitigate the possibility of DC offset effects and the image sticking problems caused by slow DC balancing rates. This invention further discloses an enabling technology for switching from one DC balance state to another without rewriting the data onto the panels. Therefore, it is not required to implement a high voltage CMOS designs and standard CMOS technologies can be applied to manufacture the storage cells and control panel for the LCOS displays with lower production cost and higher yields.

Abstract: The present invention discloses a pixel display configuration by providing a voltage controller in each pixel control circuit for controlling the voltage inputted to the pixel electrodes. The controller includes a function of multiplexing the voltage input to the pixel electrodes and also a bit buffering and decoupling function to decouple and flexible change the input voltage level to the pixel electrodes. The controller further includes a first switching stage and a second switching stage and each stage has a P-type transistor and a N-type transistor to expand the range of the switching voltages such that the improvement of the pixel control is further enhanced. The rate of DC balancing can be increased to one KHz and higher to mitigate the possibility of DC offset effects and the image sticking problems caused by slow DC balancing rates. This invention further discloses an enabling technology for switching from one DC balance state to another without rewriting the data onto the panels.

Abstract: A multiplexed pixel display includes a plurality of pixel electrodes, a plurality of storage elements, a first voltage supply terminal, a second voltage supply terminal, a common electrode, and a plurality of multiplexers each selectively coupling an associated one of the pixel electrodes with one of the first voltage supply terminal and the second voltage supply terminal responsive to a value of a data bit stored in an associated one of said storage elements. A controller is configured to sequentially write each bit of multi-bit data words to the storage elements, and assert, while each bit is stored in the storage elements, a first predetermined voltage on the first voltage supply terminal, a second predetermined voltage on the second voltage supply terminal, and a third predetermined voltage on the common electrode, for a time dependent on the significance of the stored bit. Various alternate controllers facilitate the use of additional driving schemes.

Abstract: The present invention discloses the circuit configurations and control logic to monitor the temperature of the liquid crystal as directly as possible then render and pass this data to a processing unit. The control logic in the processor then issues corrections to the voltage delivered to the liquid crystal cell to permit the liquid crystal device to continue to operate in its useful voltage range (the monotonically increasing range previously mentioned.) The object is to provide temperature control and compensation control module that would be flexibly applicable to different types of microdisplay systems. For a microdisplay system where the E-O curve decreases monotonically with increasing voltage, the control module can issue an appropriate correction signal for controlling and compensating the performance of a microdisplay as temperature variation occurs.

Abstract: A multiplexed pixel display includes a plurality of pixel electrodes, a plurality of storage elements, a first voltage supply terminal, a second voltage supply terminal, a common electrode, and a plurality of multiplexers each selectively coupling an associated one of the pixel electrodes with one of the first voltage supply terminal and the second voltage supply terminal responsive to a value of a data bit stored in an associated one of said storage elements. A controller is configured to sequentially write each bit of multi-bit data words to the storage elements, and assert, while each bit is stored in the storage elements, a first predetermined voltage on the first voltage supply terminal, a second predetermined voltage on the second voltage supply terminal, and a third predetermined voltage on the common electrode, for a time dependent on the significance of the stored bit. Various alternate controllers facilitate the use of additional driving schemes.