Abstract: A temperature control and compensation system is implemented by employing a closely coupled electrical architecture that applies the measured microdisplay temperature, one for each color channel, together with lookup tables preloaded with measured or predicted data for a display, to modify the liquid crystal voltage operating range of each microdisplay as required to achieve and maintain the proper white point operating point for the display. The electrical architecture includes functional blocks as required for realizing the temperature compensation and control for each color channel. The system microprocessor and control unit employs a lookup table to set the control registers on each microdisplay controller with values according to a computed value using the data retrieved from the lookup tables. The range of values in the lookup table includes setups for a number of varied conditions. One of these conditions is temperature.

Abstract: The present invention discloses a pixel display configuration by providing a voltage controller in each pixel control circuit for controlling the voltage inputted to the pixel electrodes. The controller includes a function of multiplexing the voltage input to the pixel electrodes and also a bit buffering and decoupling function to decouple and flexible change the input voltage level to the pixel electrodes. The controller further a delay element connected to the first and second switching stages for delaying a turning on of one stage after a turning off of another stage with sufficient delay for loading a predefined set of display data for preventing turning on of both said first and second switching stages. The rate of DC balancing can be increased to one KHz and higher to mitigate the possibility of DC offset effects and the image sticking problems caused by slow DC balancing rates.

Abstract: A multiplexed pixel display includes a plurality of pixel electrodes, a plurality of storage elements, a first voltage supply terminal, a second voltage supply terminal, a common electrode, and a plurality of multiplexers each selectively coupling an associated one of the pixel electrodes with one of the first voltage supply terminal and the second voltage supply terminal responsive to a value of a data bit stored in an associated one of said storage elements. A controller is configured to sequentially write each bit of multi-bit data words to the storage elements, and assert, while each bit is stored in the storage elements, a first predetermined voltage on the first voltage supply terminal, a second predetermined voltage on the second voltage supply terminal, and a third predetermined voltage on the common electrode, for a time dependent on the significance of the stored bit. Various alternate controllers facilitate the use of additional driving schemes.

Abstract: The present invention discloses a pixel display configuration by providing a voltage controller in each pixel control circuit for controlling the voltage inputted to the pixel electrodes. The controller includes a function of multiplexing the voltage input to the pixel electrodes and also a bit buffering and decoupling function to decouple and flexible change the input voltage level to the pixel electrodes. The controller further a delay element connected to the first and second switching stages for delaying a turning on of one stage after a turning off of another stage with sufficient delay for loading a predefined set of display data for preventing turning on of both said first and second switching stages. The rate of DC balancing can be increased to one KHz and higher to mitigate the possibility of DC offset effects and the image sticking problems caused by slow DC balancing rates.

Abstract: The present invention discloses a pixel display configuration by providing a voltage controller in each pixel control circuit for controlling the voltage inputted to the pixel electrodes. The controller includes a function of multiplexing the voltage input to the pixel electrodes and also a bit buffering and decoupling function to decouple and flexible change the input voltage level to the pixel electrodes. The rate of DC balancing can be increased to one KHz and higher to mitigate the possibility of DC offset effects and the image sticking problems caused by slow DC balancing rates. This invention further discloses an enabling technology for switching from one DC balance state to another without rewriting the data onto the panels. Therefore, it is not required to implement a high voltage CMOS designs and standard CMOS technologies can be applied to manufacture the storage cells and control panel for the LCOS displays with lower production cost and higher yields.

Abstract: The present invention discloses a pixel display configuration by providing a voltage controller in each pixel control circuit for controlling the voltage inputted to the pixel electrodes. The controller includes a function of multiplexing the voltage input to the pixel electrodes and also a bit buffering and decoupling function to decouple and flexible change the input voltage level to the pixel electrodes. The controller further includes a first switching stage and a second switching stage and each stage has a P-type transistor and a N-type transistor to expand the range of the switching voltages such that the improvement of the pixel control is further enhanced. The rate of DC balancing can be increased to one KHz and higher to mitigate the possibility of DC offset effects and the image sticking problems caused by slow DC balancing rates. This invention further discloses an enabling technology for switching from one DC balance state to another without rewriting the data onto the panels.

Abstract: A temperature control and compensation system is implemented by employing a closely coupled electrical architecture that applies the measured microdisplay temperature, one for each color channel, together with lookup tables preloaded with measured or predicted data for a display, to modify the liquid crystal voltage operating range of each microdisplay as required to achieve and maintain the proper white point operating point for the display. The electrical architecture includes functional blocks as required for realizing the temperature compensation and control for each color channel. The system microprocessor and control unit employs a lookup table to set the control registers on each microdisplay controller with values according to a computed value using the data retrieved from the lookup tables. The range of values in the lookup table includes setups for a number of varied conditions. One of these conditions is temperature.

Abstract: The present invention discloses the circuit configurations and control logic to monitor the temperature of the liquid crystal as directly as possible then render and pass this data to a processing unit. The control logic in the processor then issues corrections to the voltage delivered to the liquid crystal cell to permit the liquid crystal device to continue to operate in its useful voltage range (the monotonically increasing range previously mentioned.) The object is to provide temperature control and compensation control module that would be flexibly applicable to different types of microdisplay systems. For a microdisplay system where the E-O curve decreases monotonically with increasing voltage, the control module can issue an appropriate correction signal for controlling and compensating the performance of a microdisplay as temperature variation occurs.

Abstract: A display device and modulation scheme for applying image data to an imager. The display may use a modulation scheme wherein spacing of row write actions on the rows creates gray scale modulation, wherein one row spacing between sequential row write actions is at a first distance while another row spacing between sequential row write actions is at a distance greater than said first distance. The modulation scheme may create a series of write pointers that create a corresponding series of write planes. In some embodiments, modulation efficiency is increased allowing the use of lower frequency imaging circuits to achieve the same display image.

Abstract: A display driver circuit includes a word line sequencer for providing a series of row addresses, and a row decoder for decoding each of the row addresses and asserting write signals on corresponding ones of a plurality of output terminals. An optional data path sequencer provides a series of path addresses which are used by an optional data router to route data to particular sub-rows of a display. Additionally, an optional sub-row sequencer provides a series of sub-row addresses to an optional sub-row decoder, which decodes each of the sub-row addresses and asserts write signals on corresponding ones of a second plurality of output terminals.

Abstract: A display driver circuit for reducing system interface band width requirements and peak current requirements includes a select line sequencer, for providing a series of select line addresses on an address terminal set, and a select line decoder coupled to the address terminal set, for decoding each of the select line addresses and asserting an update signal on a corresponding one of a plurality of output terminals. Optionally, the select line sequencer generates a series of select sub-line addresses, and the select line decoder is a select sub-line decoder. An optional select address register receives initial select addresses from a system and provides the initial select addresses to the select line sequencer. An alternate display driver circuit including a select line sequencer and a select sub-line sequencer is also described.

Abstract: A display driver circuit for reducing system interface band width requirements and peak current requirements includes a select line sequencer, for providing a series of select line addresses on an address terminal set, and a select line decoder coupled to the address terminal set, for decoding each of the select line addresses and asserting an update signal on a corresponding one of a plurality of output terminals. Optionally, the select line sequencer generates a series of select sub-line addresses, and the select line decoder is a select sub-line decoder. An optional select address register receives initial select addresses from a system and provides the initial select addresses to the select line sequencer. An alternate display driver circuit including a select line sequencer and a select sub-line sequencer is also described.

Abstract: A display driver circuit includes a word line sequencer for providing a series of row addresses, and a row decoder for decoding each of the row addresses and asserting write signals on corresponding ones of a plurality of output terminals. An optional data path sequencer provides a series of path addresses which are used by an optional data router to route data to particular sub-rows of a display. Additionally, an optional sub-row sequencer provides a series of sub-row addresses to an optional sub-row decoder, which decodes each of the sub-row addresses and asserts write signals on corresponding ones of a second plurality of output terminals. In various embodiments, the row sequencer, the sub-row sequencer, and/or the data path sequencer is/are responsive to data load instructions from a system, such that no Array Write commands are required to write data to a display.

Abstract: A system and method for reducing the phase difference between adjacent gray scale values employ compound data words. The compound data words include a first group of data bits and a second group of data bits. A display driver circuit is configured to provide display control signals causing each bit of the first group of data bits to be asserted on the display pixel for a coequal time period, and causing each bit of the second group of data bits to be asserted on the display pixel for a time period dependent on an associated significance of each bit. Optionally, the display driver circuit further includes a compound data generator configured to provide the compound data words. A method for asserting a compound data word on a display pixel includes the steps of asserting each bit of the first group of bits on the display pixel for a coequal time period, and asserting each bit of the second group of bits on the display pixel for a time period dependent on an associated significance of each bit.

Abstract: A method for displaying multi-bit data words on a display including a plurality of pixel electrodes, a plurality of storage elements, a first voltage supply terminal, a second voltage supply terminal, a common electrode, and a plurality of multiplexers each selectively coupling an associated one of the pixel electrodes with one of the first voltage supply terminal and the second voltage supply terminal responsive to a value of a data bit stored in an associated one of said storage elements, includes the steps of sequentially writing each bit of the multi-bit data words to the storage elements, and asserting, while each bit is stored in the storage elements, a first predetermined voltage on the first voltage supply terminal, a second predetermined voltage on the second voltage supply terminal, and a third predetermined voltage on the common electrode, for a time dependent on the significance of the stored bit.

Abstract: A display includes a pair of global voltage supply terminals, for providing predetermined voltages, and a plurality of pixel cells. Each pixel cell includes a pixel electrode, a storage element for storing a data bit, and a multiplexer for selectively coupling the pixel electrode with one or the other of the global voltage supply terminals, depending on the value of the stored data bit. A voltage controller asserts predetermined voltages on the global voltage supply terminals, which are then transferred to the coupled pixel electrodes.