Abstract: A liquid cooled semiconductor package and method for forming a liquid cooled semiconductor package is described. The device includes at least one semiconductor device mounted on a substrate. An impermeable housing is disposed on the substrate with an internal cavity. A liquid coolant is within the internal cavity such that the coolant immerses at least one semiconductor device.

Abstract: A cognitive learning device includes inputs with each including an input path having a transistor device having a storage capacity. A circuit is responsive to the inputs and selects an input set in accordance with a current task, wherein the input set selected modifies a characteristic of the transistor device of one or more corresponding input paths to bias the input set for selection for subsequent accesses.

Abstract: A method includes electrically joining two or more semiconductor chips to a silicon bridge chip, and electrically joining the two or more semiconductor chips to a substrate structure, the silicon bridge chip extends into a recess in the substrate structure such that a top surface of the silicon bridge chip is substantially flush with a top surface of the substrate structure.

Abstract: An integrated circuit includes pads formed on a back end of the line surface, and decoupling capacitor stacks monolithically formed about the pads. Solder balls are formed on the pads and connect to metal layers within the decoupling capacitor stacks to reduce noise and voltage spikes between the solder balls.

Abstract: A method for connecting metal layers in a mixed wire structure for a semiconductor substrate. A lower metal layer and a via in the mixed wired structure is formed in a dielectric structure on the semiconductor substrate, wherein a layer of a barrier metal is absent between the lower metal layer and the via. A trench is formed in the dielectric structure for an upper metal layer that contacts the via. A barrier metal layer is formed on the via and in the trench. The upper metal layer is formed after forming the barrier metal layer, wherein the barrier metal layer is located between the via and the upper metal layer.

Abstract: A method is presented for fine-tuning a threshold voltage of a nanosheet structure. The method includes forming a nanosheet stack over a substrate including a plurality of sacrificial layers and a plurality of nanowires, forming a sacrificial gate structure over the nanosheet stack, and partially etching one or more sacrificial layers to form cavities, the partial etching resulting in remaining sections of sacrificial layers. The method includes removing the sacrificial gate structure, removing at least one of the remaining sections of sacrificial layers to expose a surface of each of the plurality of nanowires, forming an oxidation channel on the exposed surface on only either a top side or bottom side of each of the plurality of nanowires, removing the oxidation channels to form a recess on each of the plurality of nanowires, and depositing a high-k metal gate extending into the recess of each of the plurality of nanowires.

Abstract: Devices and methods for forming a tight pitch stack nanowire without shallow trench isolation including a base nanosheet formed on a substrate. At least one fin are formed, and at least one dummy gate is formed over the at least two fins, on the base nanosheet, the at least two fins including at least two alternating layers of a first material and a second material. The base nanosheet is replaced with a blanket dielectric to form a shallow trench isolation (STI) around the at least one fin and around the at least one dummy gate. A gate replacement is performed to replace the at least one dummy gate and the second material with a gate conductor material and a gate cap to form gate structures.

Abstract: A method is presented for fine-tuning a threshold voltage of a nanosheet structure. The method includes forming a nanosheet stack over a substrate including a plurality of sacrificial layers and a plurality of nanowires, forming a sacrificial gate structure over the nanosheet stack, and partially etching one or more sacrificial layers to form cavities, the partial etching resulting in remaining sections of sacrificial layers. The method includes removing the sacrificial gate structure, removing at least one of the remaining sections of sacrificial layers to expose a surface of each of the plurality of nanowires, forming an oxidation channel on the exposed surface on only either a top side or bottom side of each of the plurality of nanowires, removing the oxidation channels to form a recess on each of the plurality of nanowires, and depositing a high-k metal gate extending into the recess of each of the plurality of nanowires.

Abstract: Devices and methods for forming a tight pitch stack nanowire without shallow trench isolation including a base nanosheet formed on a substrate. At least one fin are formed, and at least one dummy gate is formed over the at least two fins, on the base nanosheet, the at least two fins including at least two alternating layers of a first material and a second material. The base nanosheet is replaced with a blanket dielectric to form a shallow trench isolation (STI) around the at least one fin and around the at least one dummy gate. A gate replacement is performed to replace the at least one dummy gate and the second material with a gate conductor material and a gate cap to form gate structures.

Abstract: A method is presented for fine-tuning a threshold voltage of a nanosheet structure. The method includes forming a nanosheet stack over a substrate including a plurality of sacrificial layers and a plurality of nanowires, forming a sacrificial gate structure over the nanosheet stack, and partially etching one or more sacrificial layers to form cavities, the partial etching resulting in remaining sections of sacrificial layers. The method includes removing the sacrificial gate structure, removing at least one of the remaining sections of sacrificial layers to expose a surface of each of the plurality of nanowires, forming an oxidation channel on the exposed surface on only either a top side or bottom side of each of the plurality of nanowires, removing the oxidation channels to form a recess on each of the plurality of nanowires, and depositing a high-k metal gate extending into the recess of each of the plurality of nanowires.

Abstract: A cognitive learning device includes inputs with each including an input path having a transistor device having a storage capacity. A circuit is responsive to the inputs and selects an input set in accordance with a current task, wherein the input set selected modifies a characteristic of the transistor device of one or more corresponding input paths to bias the input set for selection for subsequent accesses.

Abstract: After forming a monolithically integrated device including a laser and a modulator on a semiconductor substrate, an anti-reflection coating layer is formed over the monolithically integrated device and the semiconductor substrate by an atomic layer deposition (ALD) process. The anti-reflection coating layer is lithographically patterned so that an anti-reflection coating is only present on exposed surfaces of the modulator. After forming an etch stop layer portion to protect the anti-reflection coating, a high reflection coating layer is formed over the etch stop layer, the laser and the semiconductor structure by ALD and lithographically patterned to provide a high reflection coating that is formed solely on a non-output facet of the laser.

Abstract: A method of forming an interconnect structure includes providing a first dielectric layer, patterning a wire opening in a first dielectric layer, lining the wire opening with a metal liner and includes filling the wire opening with a first conductive material. The method also includes depositing a first cap on the first dielectric layer, depositing a second dielectric layer, and patterning a via trench in the second dielectric layer. The method also includes depositing a metal liner, removing the metal liner from a via junction, and enlarging the contact area. The method also includes filling the via trench with a second conductive material to form a via.

Abstract: An integrated circuit includes pads formed on a back end of the line surface, and decoupling capacitor stacks monolithically formed about the pads. Solder balls are formed on the pads and connect to metal layers within the decoupling capacitor stacks to reduce noise and voltage spikes between the solder balls.

Abstract: A method is presented for fine-tuning a threshold voltage of a nanosheet structure. The method includes forming a nanosheet stack over a substrate including a plurality of sacrificial layers and a plurality of nanowires, forming a sacrificial gate structure over the nanosheet stack, and partially etching one or more sacrificial layers to form cavities, the partial etching resulting in remaining sections of sacrificial layers. The method includes removing the sacrificial gate structure, removing at least one of the remaining sections of sacrificial layers to expose a surface of each of the plurality of nanowires, forming an oxidation channel on the exposed surface on only either a top side or bottom side of each of the plurality of nanowires, removing the oxidation channels to form a recess on each of the plurality of nanowires, and depositing a high-k metal gate extending into the recess of each of the plurality of nanowires.

Abstract: Devices and methods for forming a tight pitch stack nanowire without shallow trench isolation including a base nanosheet formed on a substrate. At least one fin are formed, and at least one dummy gate is formed over the at least two fins, on the base nanosheet, the at least two fins including at least two alternating layers of a first material and a second material. The base nanosheet is replaced with a blanket dielectric to form a shallow trench isolation (STI) around the at least one fin and around the at least one dummy gate. A gate replacement is performed to replace the at least one dummy gate and the second material with a gate conductor material and a gate cap to form gate structures.

Abstract: An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins.

Abstract: A multi-chip module includes a first semiconductor component including a first set of connections having a first pitch dimension and at least a second set of connections having a second pitch dimension, wherein the first pitch dimension is smaller than the second pitch dimension. The multi-chip module further includes a second semiconductor component interconnected with the first set of connections of the first semiconductor component. The multi-chip module further includes at least a third semiconductor component interconnected with the second set of connections of the first semiconductor component and wherein a surface of the third semiconductor component is adhered to a surface of the second semiconductor component, wherein the surfaces at least partially overlap one another.

Abstract: Non-planar field effect transistor (FET) devices having wrap-around source/drain contacts are provided, as well as methods for fabricating non-planar FET devices with wrap-around source/drain contacts. A method includes forming a non-planar FET device on a substrate, which includes a semiconductor channel layer, and a gate structure in contact with upper and sidewall surfaces of the semiconductor channel layer. First and second source/drain regions are formed on opposite sides of the gate structure in contact with the semiconductor channel layer. First and second recesses are formed in an isolation layer below bottom surfaces of the first and second source/drain regions, respectively. A layer of metallic material is deposited to fill the first and second recesses in the isolation layer with metallic material and form first and second source/drain contacts which surround the first and second source/drain regions.

Abstract: Non-planar field effect transistor (FET) devices having wrap-around source/drain contacts are provided, as well as methods for fabricating non-planar FET devices with wrap-around source/drain contacts. A method includes forming a non-planar FET device on a substrate, which includes a semiconductor channel layer, and a gate structure in contact with upper and sidewall surfaces of the semiconductor channel layer. First and second source/drain regions are formed on opposite sides of the gate structure in contact with the semiconductor channel layer. First and second recesses are formed in an isolation layer below bottom surfaces of the first and second source/drain regions, respectively. A layer of metallic material is deposited to fill the first and second recesses in the isolation layer with metallic material and form first and second source/drain contacts which surround the first and second source/drain regions.