Abstract: A method includes electrically joining two or more semiconductor chips to a silicon bridge chip, and electrically joining the two or more semiconductor chips to a substrate structure, the silicon bridge chip extends into a recess in the substrate structure such that a top surface of the silicon bridge chip is substantially flush with a top surface of the substrate structure.

Abstract: A method of forming a III-V semiconductor vertical fin is provided. The method includes forming a fin mandrel on a substrate, forming a spacer layer on the substrate surrounding the fin mandrel, forming a wetting layer on each of the sidewalls of the fin mandrel, forming a fin layer on each of the wetting layers, removing the fin mandrel, removing the wetting layer on each of the fin layers, and forming a fin layer regrowth on each of the sidewalls of the fin layers exposed by removing the wetting layer from each of the fin layers.

Abstract: Non-planar field effect transistor (FET) devices having wrap-around source/drain contacts are provided, as well as methods for fabricating non-planar FET devices with wrap-around source/drain contacts. A method includes forming a non-planar FET device on a substrate, which includes a semiconductor channel layer, and a gate structure in contact with upper and sidewall surfaces of the semiconductor channel layer. First and second source/drain regions are formed on opposite sides of the gate structure in contact with the semiconductor channel layer. First and second recesses are formed in an isolation layer below bottom surfaces of the first and second source/drain regions, respectively. A layer of metallic material is deposited to fill the first and second recesses in the isolation layer with metallic material and form first and second source/drain contacts which surround the first and second source/drain regions.

Abstract: A metal strap is formed in a middle-of-line (MOL) process for communication between an eDRAM and a FinFET. An oxide is deposited in a trench over the eDRAM to prevent development of an epitaxial film prior to formation of the metal strap. The result is an epiless eDRAM strap in a FinFET.

Abstract: A floating gate setup method, system, and computer program product include, in an initial setup of weights for a floating gate including rows, columns, and a separate input line: comparing a current weight to a desired weight, performing a feedback to the input line to set a voltage to change the floating gate FET VT and the current weight, and checking that the current weight is within a predetermined tolerance of the desired weight.

Abstract: A method of forming a III-V semiconductor vertical fin is provided. The method includes forming a fin mandrel on a substrate, forming a spacer layer on the substrate surrounding the fin mandrel, forming a wetting layer on each of the sidewalls of the fin mandrel, forming a fin layer on each of the wetting layers, removing the fin mandrel, removing the wetting layer on each of the fin layers, and forming a fin layer regrowth on each of the sidewalls of the fin layers exposed by removing the wetting layer from each of the fin layers.

Abstract: A method of forming a pair of edge-emitting lasers is provided. The method includes forming a mesa from a substrate, forming a cover layer on the substrate around the mesa, and forming a first barrier layer on each of opposite sidewalls of the mesa. The method further includes forming a quantum well layer on each of the barrier layers, forming a second barrier layer on each of the quantum well layers, and forming a cladding layer on each of the second barrier layers.

Abstract: Semiconductor devices and methods are provided to fabricate FET devices having overlapping gate and source/drain contacts while preventing electrical shorts between the overlapping gate and source/drain contacts. For example, a semiconductor device includes a plurality of semiconductor fins patterned in a starting semiconductor substrate; a set of gate structures formed on the starting semiconductor substrate; a set of spacers formed around each of the set of gate structures; a source and drain region grown around the plurality of fins; a conductive metal material on the source and drain region, an insulating material is configured to be deposited over an upper surface of the conductive metal material and the gate structure; and a plurality of contacts in the insulator material. The plurality of contacts is formed such that a bottom surface of the plurality of contacts is in contact with at least a portion of the upper surface of the gate structure.

Abstract: An approach is provided in which an information handling system performs multiple tests on a memory device using different supply voltage levels. The information handling system identifies a set of memory cells in the memory that produce a same result during each of the memory tests at the different supply voltage levels, and generates a unique identifier based on the set of memory cells. In turn, the information handling system uses the unique identifier in one or more processes executed by the information handling system.

Abstract: A structure includes an optoelectronic device having a Group IV substrate (e.g., Si); a buffer layer (e.g. SiGe) disposed on the substrate and a first distributed Bragg reflector (DBR) disposed on the buffer layer. The first DBR contains alternating layers of doped Group IV materials (e.g., alternating layers of SiyGe(1-y), where 0.8<y<1, and SizGe(1-z), where 0.2<z<0.4) that are substantially transparent to a wavelength of interest. The structure further includes a strained layer of a Group III-V material over the first DBR and a second DBR over the strained layer. The second DBR contains alternating layers of electrically conductive oxides (e.g., ITO/AZO) that are substantially transparent to the wavelength of interest. Embodiments of VCSELs and photodetectors can be derived from the structure. The strained layer of Group III-V material can be, for example, a thin layer of In0.53Ga0.47As having a thickness in a range of about 2 nm to about 5 nm.

Abstract: A single chip including an optoelectronic device on the semiconductor layer in a first region, the optoelectronic device comprises a bottom cladding layer, an active region, and a top cladding layer, wherein the bottom cladding layer is above and in direct contact with the semiconductor layer, the active region is above and in direct contact with the bottom cladding layer, and the top cladding layer is above and in direct contact with the active region, a silicon device on the substrate extension layer in a second region, a device insulator layer substantially covering both the optoelectronic device in the first region and the silicon device in the second region, and a waveguide embedded within the device insulator layer in direct contact with a sidewall of the active region of the optoelectronic device.

Abstract: A semiconductor device includes a source region and a drain region formed in a transistor structure. A channel region is disposed between the source region and the drain region. A cladding layer is formed on the channel region, the cladding layer including a semiconductor material. A gate dielectric of a gate structure is formed on the cladding layer.

Abstract: A structure and method for fabricating a vertical heterojunction tunnel field effect transistor (TFET) using limited lithography steps is disclosed. The fabrication of a second conductivity type source/drain region may utilize a single lithography step to form a first-type source/drain region, and a metal contact thereon, adjacent to a gate stack having a first conductivity type source/drain region on an opposite side.

Abstract: Weights of a neural network are initialized by programming a plurality of unit cells. A given one of the plurality of unit cells includes one or more static random-access memory cells and a digital to analog converter device. The digital to analog converter device is configured to receive one or more outputs produced by respective ones of the one or more static random-access memory cells. An amount of error associated with the initialized weights is determined. The initialized weights are adjusted in response to the amount of error exceeding a threshold amount of error.

Abstract: A method of forming the fin structure that includes forming a replacement gate structure on a channel region of the at least one replacement fin structure; and forming an encapsulating dielectric encapsulating the replacement fin structure leaving a portion of the replacement gate structure exposed. The exposed portion of the replacement gate structure is etched to provide an opening through the encapsulating dielectric to the replacement fin structure. The replacement fin structure is etched selectively to the dielectric to provide a fin opening having a geometry dictated by the encapsulating dielectric. Functional fin structures of a second semiconductor material is epitaxially grown on the growth surface of the substrate substantially filling the fin opening.

Abstract: A method of forming a nanowire heterostructure, including, forming a dummy nanowire on a substrate, forming a sacrificial cover layer on the dummy nanowire, forming a spacer layer on a portion of the sacrificial cover layer, wherein a portion of the sacrificial cover layer extends above the top surface of the spacer layer, removing the portion of the sacrificial cover layer that extends above the top surface of the spacer layer, forming a gate structure on the spacer layer and a remaining portion of the sacrificial cover layer, forming an interlayer dielectric (ILD) layer on the gate structure, removing the dummy nanowire to form a nanowire trench, and forming a replacement nanowire in the nanowire trench

Abstract: A vertical FET with asymmetrically positioned source region and drain region is provided. The source region of the vertical FET is separated from a gate electrode by a gate dielectric and the drain region of the vertical FET is separated from the gate electrode by a drain spacer formed therebetween.

Abstract: An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins.

Abstract: A nanopore FET sensor device and method of making. The nanopore FET sensor device includes a FET device stack of material layers including a source, channel and drain layers, and a nanoscale hole through the FET device stack to permit flow of strands of molecular material, e.g., DNA, therethrough. The perimeter of the nanoscale hole forms a FET device gate surface. The source and drain layers are provided with respective contacts for connection with measuring instruments that measure a flow of current therebetween. The molecular strands having charged portions pass from one side of a wafer substrate to the other side through the (nanopore) gate and modulate the current flow sensed at the source or drain terminals. The sensor collects real-time measurements of the current flow modulations for use in identifying the type of molecule. Multiple measurements by the same nanopore FET sensor are collected and compared for enhanced detection.

Abstract: A U-shaped gate dielectric structure is provided that has a horizontal gate dielectric portion having a vertical thickness, and a vertical gate dielectric wall portion extending upwards from the horizontal gate dielectric portion. The vertical gate dielectric wall portion has a lateral thickness that is greater than the vertical thickness of the horizontal gate dielectric portion. The U-shaped gate dielectric structure houses a gate conductor portion. Collectively, the U-shaped gate dielectric structure and the gate conductor portion provide a functional gate structure that has reduced capacitance.