Abstract: A method that allows integrating complementary metal oxide semiconductor (CMOS) transistors and a non-volatile memory (NVM) transistor on a single substrate is provided. The NVM transistor includes a gate stack containing a high-k tunneling gate dielectric, a floating gate electrode, a high-k control gate dielectric and a control gate electrode. The high-k tunneling gate dielectric is formed form a first high-k dielectric layer employed in formation of a gate dielectric for a p-type field effect transistor (FET), the floating gate electrode is formed from a capping material layer employed in annealing the first high-k dielectric layer, and the high-k control gate dielectric is formed from a second high-k dielectric layer employed in formation of a gate dielectric for an n-type FET.

Abstract: A semiconductor structure is provided that can be used for DNA sequencing detection. The semiconductor structure includes a doped epitaxial source semiconductor material structure located on a first portion of a semiconductor substrate and a doped epitaxial drain semiconductor material structure located on a second portion of the semiconductor substrate. A gate dielectric portion is located on a third portion of the semiconductor substrate and positioned between the doped epitaxial source semiconductor material structure and the doped epitaxial drain semiconductor material structure. A non-stick nucleotide, DNA and DNA polymerase material structure is located atop the doped epitaxial source semiconductor material structure and atop the doped epitaxial drain semiconductor material structure, wherein a cavity is present in the non-stick nucleotide, DNA and DNA polymerase material structure that exposes a topmost surface of the gate dielectric portion.

Abstract: A method of forming the fin structure that includes forming a replacement gate structure on a channel region of the at least one replacement fin structure; and forming an encapsulating dielectric encapsulating the replacement fin structure leaving a portion of the replacement gate structure exposed. The exposed portion of the replacement gate structure is etched to provide an opening through the encapsulating dielectric to the replacement fin structure. The replacement fin structure is etched selectively to the dielectric to provide a fin opening having a geometry dictated by the encapsulating dielectric. Functional fin structures of a second semiconductor material is epitaxially grown on the growth surface of the substrate substantially filling the fin opening.

Abstract: A semiconductor device includes a stack of layers stacked vertically and including a source layer, a drain layer and a channel layer between the source layer and the drain layer. A gate electrode is formed in a common plane with the channel layer and a gate dielectric is formed vertically between the gate electrode and the channel layer. A first contact contacts the stack of layers on a first side of the stack of layers, and a second contact formed on an opposite side vertically from the first contact.

Abstract: A vertical injection punchthrough based metal oxide semiconductor (VIPMOS) device and method of manufacturing the same, include a control gate, an erase gate, a floating gate, and an active area where the control gate, the erase gate, and the floating gate are coplanar and perpendicular to the active area.

Abstract: A floating gate setup method, system, and computer program product include, in an initial setup of weights for a floating gate including rows, columns, and a separate input line: comparing a current weight to a desired weight, performing a feedback to the input line to set a voltage to change the floating gate FET VT and the current weight, and checking that the current weight is within a predetermined tolerance of the desired weight.

Abstract: A method for forming a floating gate memory cell includes: forming an active region on a semiconductor substrate; forming a gate stack on the active region, the gate stack including a first gate layer defining a floating gate of the memory cell structure, a dielectric layer formed on the first gate layer, and a second gate layer defining a control gate of the memory cell structure formed on the dielectric layer; forming first and second source/drain regions in the active region, self-aligned with the gate stack; forming an erase/injection gate on at least a portion of the dielectric layer and spaced laterally from the control gate, the erase/injection gate being proximate to and above the floating gate; and forming multiple contacts providing electrical connection with the first and second source/drain regions, the control gate and the erase/injection gate.

Abstract: A semiconductor device with one or more fin structures formed from a first material, gate, source, and drain regions formed from a second material, and a contact insulator layer deposited over the substrate, where an etching process applied to the substrate removes the insulator to create a trench over the source region. The device also includes a lower band gap source material that is deposited into the trench, a second contact insulator layer, and a metalizing material that is deposited over the substrate. In some embodiments, the device also includes a higher band gap source material that is deposited into the trench, a second contact insulator layer, and a metalizing material that is deposited over the substrate.

Abstract: A nanowire structure includes successive crystalline nanowire segments formed over a semiconductor substrate. A first crystalline segment formed directly on the semiconductor substrate provides electrical isolation between the substrate and the second crystalline segment. Second and fourth crystalline segments are each formed from a p-type or an n-type semiconductor material, while the third crystalline segment is formed from a semiconductor material that is oppositely doped with respect to the second and fourth crystalline segments.

Abstract: After forming a monolithically integrated device including a laser and a modulator on a semiconductor substrate, an anti-reflection coating layer is formed over the monolithically integrated device and the semiconductor substrate by an atomic layer deposition (ALD) process. The anti-reflection coating layer is lithographically patterned so that an anti-reflection coating is only present on exposed surfaces of the modulator. After forming an etch stop layer portion to protect the anti-reflection coating, a high reflection coating layer is formed over the etch stop layer, the laser and the semiconductor structure by ALD and lithographically patterned to provide a high reflection coating that is formed solely on a non-output facet of the laser.

Abstract: A method of making a dual isolation fin comprises applying a mask to a substrate and etching the exposed areas of the substrate to form a mandrel; forming a dielectric layer on the surface of the substrate and adjacent to the mandrel; forming a first epitaxially formed material on the exposed portions of the mandrel; forming a second epitaxially formed material on the first epitaxially formed material; forming a first isolation layer on the dielectric layer and adjacent to the second epitaxially formed material; removing the mask and mandrel after forming the first isolation layer; removing the first epitaxially formed material after removing the mask and mandrel; and forming a second isolation layer.

Abstract: A neural network unit cell circuit includes multiple floating gate transistors, each of the floating gate transistors having a first source/drain adapted for connection to a common bit line coupled with the unit cell circuit and having a gate adapted for connection to a corresponding one of a plurality of word lines coupled with the unit cell circuit. The unit cell further includes a resistor network having a plurality of resistors connected in a series ladder arrangement, with each node between adjacent resistors operatively connected to a second source/drain of a corresponding one of the floating gate transistors. The resistor network has a first terminal connected to a first voltage source. A readout transistor in the unit cell has a gate coupled with a second terminal of the resistor network, and has first and second source/drains generating an output voltage of the unit cell.

Abstract: Semiconductor devices and methods are provided to fabricate field effect transistor (FET) devices having local wiring between the stacked devices. For example, a semiconductor device includes a first FET device on a semiconductor substrate, the FET device comprising a first source/drain layer, and a first gate structure comprising a gate dielectric layer and a metal gate layer. The semiconductor device further includes a second FET device comprising a second source/drain layer, and a second gate structure comprising a gate dielectric layer and a metal gate layer; wherein the first and second FET devices are in a stacked configuration. The semiconductor device further includes one or more conductive vias in communication with either the first gate structure of the first FET device or the second gate structure of the second FET device.

Abstract: A method including patterning a continuous fin having a first segment and a second segment in a semiconductor layer, the first segment is arranged at an angle relative to the second line segment, and forming a first gate and a second gate substantially parallel to each other, the first gate substantially covering sides and a top of a portion of the first segment of the continuous fin, the second gate substantially covering sides and a top of a portion of the second segment of the continuous fin.

Abstract: A memory device including a plurality of memory unit cells arranged in a crossbar configuration for a neural network is provided. Each of the memory unit cells includes a readout transistor, a charging transistor, a discharging transistor, and a metal-insulator-metal (MIM) capacitor connected to one of source/drain regions of each of the charging transistor and the discharging transistor and a functional gate of the readout transistor for storing analog information.

Abstract: A method for use in forming a fin of a field-effect transistor includes: patterning a mandrel into a substrate at least by recessing portions of the substrate; forming dielectric material at least on the recessed portions of the substrate, wherein the dielectric material partially covers exterior sidewalls of the mandrel; forming a first buffer at least on a portion of the exterior sidewalls of the mandrel not covered by the dielectric material; forming a second buffer at least on exterior sidewalls of the first buffer; forming a semiconductor channel at least on the dielectric material, wherein at least the second buffer is between the channel and the mandrel; exposing interior sidewalls of at least the first buffer at least by removing the mandrel; and removing the first buffer and the second buffer without removing the channel.

Abstract: A multi-chip module structure (MCM) having improved heat dissipation includes a plurality of semiconductor chips having a front side mounted on a packaging substrate, wherein each semiconductor chip of the plurality of semiconductor chips further includes a through-substrate vias located at a backside of each semiconductor chip of the plurality of semiconductor chips. A plurality of wire bonds is present that provides interconnect between each semiconductor chip of the plurality of semiconductor chips and is located at the backside of each semiconductor chip of the plurality of semiconductor chips. A heat sink is located above a gap containing the plurality of wire bonds, and a cooling element is located on a surface of the heat sink.

Abstract: A method of forming a semiconductor structure includes depositing a high-k dielectric layer within a first recess located between sidewall spacers of a first CMOS device and within a second recess located between sidewall spacers of a second CMOS device. A dummy titanium nitride layer is deposited on the high-k dielectric layer. Next, the high-k dielectric layer and the dummy titanium nitride layer are removed from the second recess in the second CMOS device. A silicon cap layer is deposited within the first recess and the second recess, the silicon cap layer is located above the high-k dielectric layer and dummy titanium nitride layer in the first CMOS device. Subsequently, dopants are implanted into the silicon cap layer located in the second recess of the second CMOS device.

Abstract: In one example, a method for fabricating a semiconductor device includes forming a mandrel comprising silicon. Sidewalls of the silicon are orientated normal to the <111> direction of the silicon. A nanowire is grown directly on at least one of the sidewalls of the silicon and is formed from a material selected from Groups III-V. Only one end of the nanowire directly contacts the silicon.

Abstract: After forming an interlevel dielectric (ILD) layer over a semiconductor material portion located on a substrate, a gate trench is formed extending through the ILD layer to expose a channel region of the semiconductor material portion. A gate structure is then formed within the gate trench. Epitaxial semiconductor regions are subsequently formed within source/drain contact openings formed on opposite sides of the gate structure, followed by forming source/drain contact structures on the epitaxial semiconductor regions.