Abstract: A glass panel unit includes: a first panel including a glass pane; a second panel including another glass pane; a sealing portion; an exhaust port; and a printed portion. The second panel is arranged to face the first panel. The sealing portion is formed in a frame shape and hermetically bonds respective peripheral edge portions of the first and second panels to create an evacuated, hermetically sealed space between the first panel and the second panel. The exhaust port is provided for one panel selected from the first and second panels. A port sealing member hermetically seals the exhaust port. The printed portion is provided for the other panel selected from the first and second panels. The printed portion is located in an area, facing the exhaust port, of one surface of the other panel. The one surface either faces toward, or faces away from, the hermetically sealed space.

Abstract: A sealing head includes a frame, an intake unit, a pressing pin, and a non-contact heater. The frame is configured to be detachably attached to a work in progress of a glass panel unit. The intake unit, the pressing pin, and the non-contact heater are supported by the frame. The work in progress includes a first substrate, a second substrate, a bonding part, and an internal space. The first substrate has an evacuation port. The bonding part bonds the first substrate and the second substrate together. The internal space is formed by being surrounded by the first substrate, the second substrate, and the bonding part. The internal space is communicated with the evacuation port. The pressing pin is configured to press, toward the second substrate, a sealing material which is heat fusible and which is inserted into the evacuation port. The non-contact heater is configured to locally heat the sealing material in a non-contact manner via the second substrate.

Abstract: A glass panel unit includes: a pair of glass panels arranged to face each other; and a frame member disposed between the pair of glass panels to hermetically bond the pair of glass panels together. The frame member includes: a body; and a reinforcing portion. The body has a frame shape and includes: a first part containing a first sealing material having a first softening point; and a second part containing a second sealing material having a second softening point that is higher than the first softening point. The reinforcing portion contains a third sealing material having a third softening point that is higher than the first softening point. The reinforcing portion is adjacent to the first part in a space surrounded with the pair of glass panels and the body.

Abstract: A glass panel unit manufacturing method includes a bonding step, an insertion step, an evacuation step, and a sealing step. The bonding step includes bonding a first substrate having an evacuation port and a second substrate with a bonding material having a frame shape to form an internal space. The insertion step includes inserting a sealing material into the evacuation port. The evacuation step includes evacuating the internal space by connecting an exhaust device to the evacuation port and driving the exhaust device. The sealing step includes sealing the evacuation port with the sealing material while an evacuated state in the internal space is maintained. In the sealing step, a measured value by a pressure gauge is monitored while the sealing material is heated, softening of the sealing material is detected based on the transition of the measured value, and heating of the sealing material is stopped.

Abstract: A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has a maximum variation width of a threshold voltage for memorizing an information set larger than that of the second nonvolatile memory area. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information, and the second nonvolatile memory area can be prioritized to guarantee the number of times of rewrite operation of memory information.

Abstract: A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information, and the second nonvolatile memory area can be prioritized to guarantee the number of times of rewrite operation of memory information more.

Abstract: A method for processing a separation and rupture portion of a display label is a method for forming, on the display label attached to an attachment target object, the separation and rupture portion for rupturing the display label upon separation of the display label from the attachment target object. This method includes attaching, to the attachment target object, the display label having a back side on which an adhesive layer is formed, and then forming a slit serving as the separation and rupture portion on the display label.

Abstract: A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed In an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior In a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited.

Abstract: A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed In an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior In a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited.

Abstract: A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior in a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited.

Abstract: A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior in a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited.

Abstract: A microcomputer capable of on-board programming of dedicated user communication protocols without requiring a serial interface on the mounted board, and that will not destroy the dedicated user communication protocol code even if the system runs out of control. A user boot mat other than a user mat is provided for programming control programs for the user in the on-chip non-volatile memory of the microcomputer. The user boot mat serves as the mat for programming the dedicated user communication protocol and also provides a user boot mode for running the program. The user boot mat cannot program or erase in this user boot mode. By separating the user boot mat and user mat, an interface capable of programming and erasing the user-specified programming can be achieved without having to program a dedicated communication protocol on the user mat.

Abstract: A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior in a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited.

Abstract: A method for processing a separation and rupture portion of a display label is a method for forming, on the display label attached to an attachment target object, the separation and rupture portion for rupturing the display label upon separation of the display label from the attachment target object. This method includes attaching, to the attachment target object, the display label having a back side on which an adhesive layer is formed, and then forming a slit serving as the separation and rupture portion on the display label.

Abstract: In a motorcycle, the vehicle body frame includes main frames which are inclined rearwardly and downwardly directly towards a rear portion of a vehicle body from a head pipe with the engine being arranged close to an inclined portion of the vehicle body frame and the fuel injection device is overlapped to the main frames. In a fuel injection type engine including a cylinder head, a throttle body has an intake passage leading to an intake port and a fuel injection valve which injects fuel towards the intake port, the throttle body can be arranged close to a cylinder head and, at the same time, the fuel injection valve can be cooled effectively. A connecting sleeve portion projects further outwardly relative to a joint portion of a cylinder head and a head cover and forms an inlet portion of an intake port that is integrally formed with the cylinder head.

Abstract: A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior in a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited.

Abstract: A data processing apparatus supplied a first voltage from outside, includes a CPU, a first voltage generating circuit, a second voltage generating circuit, a clock generating circuit, and, a nonvolatile memory which can be accessed by the CPU. The first voltage generating circuit generates a second voltage, a voltage level of which is lower than that of the first voltage. The clock generating circuit is supplied the second voltage from the first voltage generating circuit and generates a clock signal, and the second voltage generating circuit is supplied the second voltage from the first voltage generating circuit and the clock signal from the clock generating circuit, and generates a second voltage, a voltage level of which is higher than that of the first voltage, for supplying to the nonvolatile memory.

Abstract: A microcomputer capable of on-board programming of dedicated user communication protocols without requiring a serial interface on the mounted board, and that will not destroy the dedicated user communication protocol code even if the system runs out of control. A user boot mat other than a user mat is provided for programming control programs for the user in the on-chip non-volatile memory of the microcomputer. The user boot mat serves as the mat for programming the dedicated user communication protocol and also provides a user boot mode for running the program. The user boot mat cannot program or erase in this user boot mode. By separating the user boot mat and user mat, an interface capable of programming and erasing the user-specified programming can be achieved without having to program a dedicated communication protocol on the user mat.

Abstract: The present invention provides a microcomputer wherein in a system which needs to respond to events developed at intervals each shorter than an erase/program process time, erase/programming can be effected on an on-chip non-volatile memory as necessary during its processing. An erase and program control program for an electrically erasable and programmable non-volatile memory is configured inclusive of a loop of the application of a high voltage pulse and data verify or the like, for example. If a program jumped to a subroutine for an address specified by a user is programmed in advance during this loop, then a process by a CPU can be temporarily jumped to the subroutine for the user defined address. Thus, erase and programming can be effected on a system which needs to confirm internal and external events every predetermined intervals or a system with a learning function, or the like during the execution of a user program.

Abstract: A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior in a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited.