Abstract: A microcomputer incorporating a flash memory which is erased and programmed electrically in a stable manner within a relatively wide range of external power supply voltages including those for low-voltage operations. The microcomputer comprises a voltage clamp unit including a reference voltage generating circuit and a constant voltage generating circuit. In operation, the voltage clamp unit generates a voltage of a low dependency on a supply voltage and clamps the generated voltage to a voltage level which, within a tolerable range, is lower than a single supply voltage externally furnished. This prevents voltages boosted by boosting circuits operating on the clamped voltage, i.e., programming and erasure voltages, from being dependent on the externally supplied voltage.

Abstract: The present invention provides a data processing system wherein the waste of use of each storage area by ECC codes is avoided to improve or increase the number of assurances for rewriting of information stored in a non-volatile memory.

Abstract: A microcomputer incorporating a flash memory which is erased and programmed electrically in a stable manner within a relatively wide range of external power supply voltages including those for low-voltage operations. The microcomputer comprises a voltage clamp unit including a reference voltage generating circuit and a constant voltage generating circuit. In operation, the voltage clamp unit generates a voltage of a low dependency on a supply voltage and clamps the generated voltage to a voltage level which, within a tolerable range, is lower than a single supply voltage externally furnished. This prevents voltages boosted by boosting circuits operating on the clamped voltage, i.e., programming and erasure voltages, from being dependent on the externally supplied voltage.

Abstract: A microcomputer incorporating a flash memory which is erased and programmed electrically in a stable manner within a relatively wide range of external power supply voltages including those for low-voltage operations. The microcomputer comprises a voltage clamp unit including a reference voltage generating circuit and a constant voltage generating circuit. In operation, the voltage clamp unit generates a voltage of a low dependency on a supply voltage and clamps the generated voltage to a voltage level which, within a tolerable range, is lower than a single supply voltage externally furnished. This prevents voltages boosted by boosting circuits operating on the clamped voltage, i.e., programming and erasure voltages, from being dependent on the externally supplied voltage.

Abstract: A method of forming a resist pattern and a method of manufacturing a semiconductor device using the method of forming the resist pattern, characterized in that a surface of an organic base coating 3 formed on an etched film 2 is reformed depending on properties of a material of a resist film 4, whereby, in dual processes for forming a lower layer of the organic coating provided to process the etched film, an amount of usable resist is increased and an accuracy of dimensions of the etched film after processing can be improved.

Abstract: A microcomputer incorporating a flash memory which is erased and programmed electrically in a stable manner within a relatively wide range of external power supply voltages including those for low-voltage operations The microcomputer comprises a voltage clamp unit including a reference voltage generating circuit and a constant voltage generating circuit. In operation, the voltage clamp unit generates a voltage of a low dependency on a supply voltage and clamps the generated voltage to a voltage level which, within a tolerable range, is lower than a single supply voltage externally furnished This prevents voltages boosted by boosting circuits operating on the clamped voltage, i.e., programming and erasure voltages, from being dependent on the externally supplied voltage.

Abstract: A first conductive layer and a second conductive layer are formed apart from each other on a surface of a semiconductor substrate. A first contact hole for exposing a surface of first conductive layer is formed in an interlayer insulating film. A first interconnection layer is buried in first contact hole so as to be in contact with first conductive layer. The position of the surface of first interconnection layer is the same as or lower than the surface of interlayer insulating film. The surface of first interconnection layer is covered with an insulating film. A second contact hole for exposing a surface of second conductive layer is provided in interlayer insulating film. A second conductive layer is connected to second conductive layer through second contact hole.

Abstract: A microcomputer incorporating a flash memory which is erased and programmed electrically in a stable manner within a relatively wide range of external power supply voltages including those for low-voltage operations. The microcomputer comprises a voltage clamp unit including a reference voltage generating circuit and a constant voltage generating circuit. In operation, the voltage clamp unit generates a voltage of a low dependency on a supply voltage and clamps the generated voltage to a voltage level which, within a tolerable range, is lower than a single supply voltage externally furnished. This prevents voltages boosted by boosting circuits operating on the clamped voltage, i.e., programming and erasure voltages, from being dependent on the externally supplied voltage.

Abstract: A single chip data processing apparatus having a central processing unit (CPU) and a flash memory constituted by electrically rewritable nonvolatile memory cells. The flash memory can be written with data under the control of the built-in CPU in an external write operation mode of the apparatus and, also, the CPU executes a data processing operation in accordance with a data processing program in a normal operation mode. In the external write operation mode, the CPU decodes a command by executing a command analyzing program so as to determine a process to be performed to the flash memory.

Abstract: In a line configuration of each memory cell array employed in a semiconductor memory device, a pair of bit line signal input/output lines or a pair of input/output data lines for transmitting complementary signals are disposed on both sides of and adjacent the global word line so as to cancel the influence of the global word line. By these configurations, the number of shielded lines may be reduced and the width of each line and the interval between the lines are arrayed for preventing the respective lines from breaking or being short-circuited.

Abstract: A first conductive layer and a second conductive layer are formed apart from each other on a surface of a semiconductor substrate. A first contact hole for exposing a surface of first conductive layer is formed in an interlayer insulating film. A first interconnection layer is buried in first contact hole so as to be in contact with first conductive layer. The position of the surface of first interconnection layer is the same as or lower than the surface of interlayer insulating film. The surface of first interconnection layer is covered with an insulating film. A second contact hole for exposing a surface of second conductive layer is provided in interlayer insulating film. A second conductive layer is connected to second conductive layer through second contact hole.

Abstract: A data processing apparatus having a built-in flash memory and being capable of performing a rewriting operation of the built-in flash memory, by use of versatilely used PROM writer, has a CPU, an electrically rewritable nonvolatile flash memory both formed in a single semiconductor substrate, and is operable in a mode in which the built-in flash memory is rewritable in accordance with commands supplied from a PROM writer. The data processing apparatus has a command latch which is externally writable when the above-mentioned operation mode is established, a command analyzer, that is, a command decoder, and a sequence controller for controlling a sequence of a rewriting operation of the flash memory in accordance with the decoded output of the command analyzer. The command analyzer and sequence controller may be realized by the CPU.

Abstract: A level F.sub.A at a shot center of a specified shot is measured. A level F.sub.B is measured at a nonexposure region. A level difference .DELTA.F is calculated based on the level F.sub.A at the shot center and the level F.sub.B at the nonexposure region. After the level difference .DELTA.F is calculated for all the specified shots, an average value .DELTA.F.sub.ave of level differences .DELTA.F is calculated. Thereafter, focusing based on the average value .DELTA.F.sub.ave and subsequent exposure are executed for the respective shots in a step-and-repeat manner. Thereby, a focusing method in photolithography enables formation of elements having good pattern configuration even if the pattern is miniaturized to a higher extent in accordance with high integration.

Abstract: A nonvolatile semiconductor memory device having a redundancy memory cell MC-R and a memory cell MC-C.sub.0 for storing relief data for designating a memory cells MC for which the memory cell MC-R is substituted. In writing the relief data, the memory cell MC-C.sub.0 is selected by a relief bit selection circuit RSEL. The relief data that is written is initially loaded in relief data latch CLAT by the instruction of a reset signal MD2. In normal writing and reading operations, the address comparator circuit ACMP compares the relief data with the address data fed from an external unit. When they are in agreement, the redundancy memory cell MC-R is selected.

Abstract: A forming method of a fine resist pattern improve so as to form a fine pattern of high accuracy can be obtained. A positive-type photoresist 1 including naphthoquinone diazide and novolak resin is applied on a substrate. An anti-reflection film adjusted to alkalinity is applied on positive-type photoresist 1. Positive-type photoresist 1 on which anti-reflection film 9 is applied is selectively irradiated. Positive-type photoresist 1 is developed.

Abstract: The object of the invention is to provide, as an auto-changer device, a medium recording-playback device which makes it possible to improve the ease of operations for ejecting plural recording medium elements from inside the device. The device possesses a stocker in which plural MDs are stored in respective storage sections that are distinguished by identification numbers, a carrier which loads installed MDs into the stocker or ejects them from an insertion port as far as a reloading position, an eject key which sets the eject mode for the MDs, and a CPU which, in response to input of the eject key, causes MDs that are present in the device to be ejected in a set order.

Abstract: A first conductive layer and a second conductive layer are formed apart from each other on a surface of a semiconductor substrate. A first contact hole for exposing a surface of first conductive layer is formed in an interlayer insulating film. A first interconnection layer is buried in first contact hole so as to be in contact with first conductive layer. The position of the surface of first interconnection layer is the same as or lower than the surface of interlayer insulating film. The surface of first interconnection layer is covered with an insulating film. A second contact hole for exposing a surface of second conductive layer is provided in interlayer insulating film. A second conductive layer is connected to second conductive layer through second contact hole.

Abstract: When exposure light reaches a silicon oxide film, this light is multiply reflected in the silicon oxide film to spread or narrow a photoresist layer. A tungsten silicide film prevents the exposure light from reaching the silicon oxide film. This silicon oxide film is employed as a mask to selectively remove a polycrystalline silicon film and a tungsten silicide film by etching for forming a gate electrode, while the tungsten silicide film is simultaneously removed by this etching.