Patents by Inventor Eiichi Ishikawa
Eiichi Ishikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7236419Abstract: A semiconductor processing device is provided which includes a nonvolatile memory unit, a voltage generating unit, and a first terminal. The voltage generating unit generates a first voltage generated from an operation voltage provided from outside of the semiconductor processing device and provides the first voltage to the nonvolatile memory unit for storing data therein. The first terminal provides the first voltage generated by the voltage generating unit to outside of the semiconductor processing device. This first voltage provided to outside of the semiconductor processing device via the first terminal permits checking a voltage level of the first voltage and correcting this voltage level.Type: GrantFiled: March 2, 2006Date of Patent: June 26, 2007Assignee: Renesas Technology Corp.Inventors: Eiichi Ishikawa, Yasuyuki Saito, Masanao Sato, Naoki Yada, Kiyoshi Matsubara
-
Publication number: 20070130416Abstract: The present invention provides a microcomputer wherein in a system which needs to respond to events developed at intervals each shorter than an erase/program process time, erase/programming can be effected on an on-chip non-volatile memory as necessary during its processing. An erase and program control program for an electrically erasable and programmable non-volatile memory is configured inclusive of a loop of the application of a high voltage pulse and data verify or the like, for example. If a program jumped to a subroutine for an address specified by a user is programmed in advance during this loop, then a process by a CPU can be temporarily jumped to the subroutine for the user defined address. Thus, erase and programming can be effected on a system which needs to confirm internal and external events every predetermined intervals or a system with a learning function, or the like during the execution of a user program.Type: ApplicationFiled: February 7, 2007Publication date: June 7, 2007Inventors: Naoki Yada, Eiichi Ishikawa
-
Patent number: 7194571Abstract: The present invention provides a microcomputer wherein in a system which needs to respond to events developed at intervals each shorter than an erase/program process time, erase/programming can be effected on an on-chip non-volatile memory as necessary during its processing. An erase and program control program for an electrically erasable and programmable non-volatile memory is configured inclusive of a loop of the application of a high voltage pulse and data verify or the like, for example. If a program jumped to a subroutine for an address specified by a user is programmed in advance during this loop, then a process by a CPU can be temporarily jumped to the subroutine for the user defined address. Thus, erase and programming can be effected on a system which needs to confirm internal and external events every predetermined intervals or a system with a learning function, or the like during the execution of a user program.Type: GrantFiled: January 19, 2005Date of Patent: March 20, 2007Assignees: Renesas Technology Corp., Hitachi Hokkai Semiconductor, Ltd.Inventors: Naoki Yada, Eiichi Ishikawa
-
Publication number: 20060164889Abstract: A semiconductor processing device is provided which includes a nonvolatile memory unit, a voltage generating unit, and a first terminal. The voltage generating unit generates a first voltage generated from an operation voltage provided from outside of the semiconductor processing device and provides the first voltage to the nonvolatile memory unit for storing data therein. The first terminal provides the first voltage generated by the voltage generating unit to outside of the semiconductor processing device. This first voltage provided to outside of the semiconductor processing device via the first terminal permits checking a voltage level of the first voltage and correcting this voltage level.Type: ApplicationFiled: March 2, 2006Publication date: July 27, 2006Inventors: Eiichi Ishikawa, Yasuyuki Saito, Masanao Sato, Naoki Yada, Kiyoshi Matsubara
-
Patent number: 7057937Abstract: A data processing apparatus having a built-in flash memory and being capable of rewriting the built-in flash memory by use of versatilely used PROM writer has a CPU, an electrically rewritable nonvolatile flash memory both formed in a single semiconductor substrate, and is operable in a mode in which the built-in flash memory is rewritable in accordance with commands supplied from a PROM writer. The data processing apparatus has a command latch made externally writable when the above-mentioned operation mode is established, a command analyzer and a sequence controller for controlling a sequence of rewriting the flash memory in accordance with the analysis result. The command analyzer and sequence controller may be realized by the CPU.Type: GrantFiled: August 10, 1998Date of Patent: June 6, 2006Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Kiyoshi Matsubara, Masanao Sato, Hirofumi Mukai, Eiichi Ishikawa
-
Patent number: 7023729Abstract: A microcomputer incorporating a flash memory which is erased and programmed electrically in a stable manner within a relatively wide range of external power supply voltages including those for low-voltage operations. The microcomputer comprises a voltage clamp unit including a reference voltage generating circuit and a constant voltage generating circuit. In operation, the voltage clamp unit generates a voltage of a low dependency on a supply voltage and clamps the generated voltage to a voltage level which, within a tolerable range, is lower than a single supply voltage externally furnished. This prevents voltages boosted by boosting circuits operating on the clamped voltage, i.e., programming and erasure voltages, from being dependent on the externally supplied voltage.Type: GrantFiled: December 7, 2004Date of Patent: April 4, 2006Assignee: Renesas Technology Corp.Inventors: Eiichi Ishikawa, Yasuyuki Saito, Masanao Sato, Naoki Yada, Kiyoshi Matsubara
-
Publication number: 20050281113Abstract: A data processing system (1) has an erasable and programmable non-volatile memory (5) and a central processing unit (2). The central processing unit allows only a specified partial storage area (20Ba) of the non-volatile memory to be intended for a software ECC process. Since ECC codes are added to the partial storage area alone and an error correction is made thereto to thereby increase the number of rewrite assurances, substantially needless waste of each storage area by ECC codes can b avoided as compared with a configuration in which the ECC codes are added to all the write data without distinction regardless of the storage areas. Further, since software copes with ECC processing, ECC correcting capability matched with a device characteristic of the non-volatile memory can easily be selected.Type: ApplicationFiled: August 10, 2005Publication date: December 22, 2005Inventors: Naoki Yada, Eiichi Ishikawa, Mitsuru Hiraki, Shoji Shukuri
-
Patent number: 6941505Abstract: A data processing system (1) has an erasable and programmable non-volatile memory (5) and a central processing unit (2). The central processing unit allows only a specified partial storage area (20Ba) of the non-volatile memory to be intended for a software ECC process. Since ECC codes are added to the partial storage area alone and an error correction is made thereto to thereby increase the number of rewrite assurances, substantially needless waste of each storage area by ECC codes can be avoided as compared with a configuration in which the ECC codes are added to all the write data without distinction regardless of the storage areas. Further, since software copes with ECC processing, ECC correcting capability matched with a device characteristic of the non-volatile memory can easily be selected.Type: GrantFiled: August 27, 2001Date of Patent: September 6, 2005Assignee: Hitachi, Ltd.Inventors: Naoki Yada, Eiichi Ishikawa, Mitsuru Hiraki, Shoji Shukuri
-
Publication number: 20050122777Abstract: The present invention provides a microcomputer wherein in a system which needs to respond to events developed at intervals each shorter than an erase/program process time, erase/programming can be effected on an on-chip non-volatile memory as necessary during its processing. An erase and program control program for an electrically erasable and programmable non-volatile memory is configured inclusive of a loop of the application of a high voltage pulse and data verify or the like, for example. If a program jumped to a subroutine for an address specified by a user is programmed in advance during this loop, then a process by a CPU can be temporarily jumped to the subroutine for the user defined address. Thus, erase and programming can be effected on a system which needs to confirm internal and external events every predetermined intervals or a system with a learning function, or the like during the execution of a user program.Type: ApplicationFiled: January 19, 2005Publication date: June 9, 2005Inventors: Naoki Yada, Eiichi Ishikawa
-
Publication number: 20050094472Abstract: A microcomputer incorporating a flash memory which is erased and programmed electrically in a stable manner within a relatively wide range of external power supply voltages including those for low-voltage operations The microcomputer comprises a voltage-clamp unit including a reference voltage generating circuit and a constant voltage generating circuit. In operation, the voltage clamp unit generates a voltage of a low dependency on a supply voltage and clamps the generated voltage to a voltage level which, within a tolerable range, is lower than a single supply voltage externally furnished. This prevents voltages boosted by boosting circuits operating on the clamped voltage, i.e., programming and erasure voltages, from being dependent on the externally supplied voltage.Type: ApplicationFiled: December 7, 2004Publication date: May 5, 2005Inventors: Eiichi Ishikawa, Yasuyuki Saito, Masanao Sato, Naoki Yada, Kiyoshi Matsubara
-
Publication number: 20050091446Abstract: A microcomputer capable of on-board programming of dedicated user communication protocols without requiring a serial interface on the mounted board, and that will not destroy the dedicated user communication protocol code even if the system runs out of control. A user boot mat other than a user mat is provided for programming control programs for the user in the on-chip non-volatile memory of the microcomputer. The user boot mat serves as the mat for programming the dedicated user communication protocol and also provides a user boot mode for running the program. The user boot mat cannot program or erase in this user boot mode. By separating the user boot mat and user mat, an interface capable of programming and erasing the user-specified programming can be achieved without having to program a dedicated communication protocol on the user mat.Type: ApplicationFiled: November 5, 2004Publication date: April 28, 2005Inventors: Naoki Yada, Eiichi Ishikawa
-
Patent number: 6845046Abstract: A microcomputer incorporating a flash memory which is erased and programmed electrically in a stable manner within a relatively wide range of external power supply voltages including those for low-voltage operations. The microcomputer comprises a voltage clamp unit including a reference voltage generating circuit and a constant voltage generating circuit. In operation, the voltage clamp unit generates a voltage of a low dependency on a supply voltage and clamps the generated voltage to a voltage level which, within a tolerable range, is lower than a single supply voltage externally furnished. This prevents voltages boosted by boosting circuits operating on the clamped voltage, i.e., programming and erasure voltages, from being dependent on the externally supplied voltage.Type: GrantFiled: July 22, 2003Date of Patent: January 18, 2005Assignee: Renesas Technology Corp.Inventors: Eiichi Ishikawa, Yasuyuki Saito, Masanao Sato, Naoki Yada, Kiyoshi Matsubara
-
Publication number: 20040255909Abstract: In a motorcycle, the vehicle body frame includes main frames which are inclined rearwardly and downwardly directly towards a rear portion of a vehicle body from a head pipe with the engine being arranged close to an inclined portion of the vehicle body frame and the fuel injection device is overlapped to the main frames. In a fuel injection type engine including a cylinder head, a, throttle body has an intake passage leading to an intake port and a fuel injection valve which injects fuel towards the intake port, the throttle body can be arranged close to a cylinder head and, at the same time, the fuel injection valve can be cooled effectively. A connecting sleeve portion projects further outwardly relative to a joint portion of a cylinder head and a head cover and forms an inlet portion of an intake port that is integrally formed with the cylinder head.Type: ApplicationFiled: May 18, 2004Publication date: December 23, 2004Inventors: Masaya Kurokawa, Tomoharu Kawano, Eiichi Ishikawa, Toshinao Takigawa
-
Patent number: 6832285Abstract: A microcomputer capable of on-board programming of dedicated user communication protocols without requiring a serial interface on the mounted board, and that will not destroy the dedicated user communication protocol code even if the system runs out of control. A user boot mat other than a user mat is provided for programming control programs for the user in the on-chip non-volatile memory of the microcomputer. The user boot mat serves as the mat for programming the dedicated user communication protocol and also provides a user boot mode for running the program. The user boot mat cannot program or erase in this user boot mode. By separating the user boot mat and user mat, an interface capable of programming and erasing the user-specified programming can be achieved without having to program a dedicated communication protocol on the user mat.Type: GrantFiled: February 25, 2002Date of Patent: December 14, 2004Assignees: Renesas Technology Corp., Hitachi Hokkai Semiconductor, Ltd.Inventors: Naoki Yada, Eiichi Ishikawa
-
Patent number: 6661715Abstract: A microcomputer incorporating a flash memory which is erased and programmed electrically in a stable manner within a relatively wide range of external power supply voltages including those for low-voltage operations. The microcomputer comprises a voltage clamp unit including a reference voltage generating circuit and a constant voltage generating circuit. In operation, the voltage clamp unit generates a voltage of a low dependency on a supply voltage and clamps the generated voltage to a voltage level which, within a tolerable range, is lower than a single supply voltage externally furnished. This prevents voltages boosted by boosting circuits operating on the clamped voltage, i.e., programming and erasure voltages, from being dependent on the externally supplied voltage.Type: GrantFiled: June 4, 2002Date of Patent: December 9, 2003Inventors: Eiichi Ishikawa, Yasuyuki Saito, Masanao Sato, Naoki Yada, Kiyoshi Matsubara
-
Publication number: 20020149988Abstract: A microcomputer incorporating a flash memory which is erased and programmed electrically in a stable manner within a relatively wide range of external power supply voltages including those for low-voltage operations. The microcomputer comprises a voltage clamp unit including a reference voltage generating circuit and a constant voltage generating circuit In operation, the voltage clamp unit generates a voltage of a low dependency on a supply voltage and clamps the generated voltage to a voltage level which, within a tolerable range, is lower than a single supply voltage externally furnished This prevents voltages boosted by boosting circuits operating on the clamped voltage, i.e., programming and erasure voltages, from being dependent on the externally supplied voltage.Type: ApplicationFiled: June 4, 2002Publication date: October 17, 2002Inventors: Eiichi Ishikawa, Yasuyuki Saito, Masanao Sato, Naoki Yada, Kiyoshi Matsubara
-
Publication number: 20020144052Abstract: A microcomputer capable of on-board programming of dedicated user communication protocols without requiring a serial interface on the mounted board, and that will not destroy the dedicated user communication protocol code even if the system runs out of control. A user boot mat other than a user mat is provided for programming control programs for the user in the on-chip non-volatile memory of the microcomputer. The user boot mat serves as the mat for programming the dedicated user communication protocol and also provides a user boot mode for running the program. The user boot mat cannot program or erase in this user boot mode. By separating the user boot mat and user mat, an interface capable of programming and erasing the user-specified programming can be achieved without having to program a dedicated communication protocol on the user mat.Type: ApplicationFiled: February 25, 2002Publication date: October 3, 2002Applicant: Hitachi, Ltd.Inventors: Naoki Yada, Eiichi Ishikawa
-
Publication number: 20020144053Abstract: The present invention provides a microcomputer wherein in a system which needs to respond to events developed at intervals each shorter than an erase/program process time, erase/programming can be effected on an on-chip non-volatile memory as necessary during its processing. An erase and program control program for an electrically erasable and programmable non-volatile memory is configured inclusive of a loop of the application of a high voltage pulse and data verify or the like, for example. If a program jumped to a subroutine for an address specified by a user is programmed in advance during this loop, then a process by a CPU can be temporarily jumped to the subroutine for the user defined address. Thus, erase and programming can be effected on a system which needs to confirm internal and external events every predetermined intervals or a system with a learning function, or the like during the execution of a user program.Type: ApplicationFiled: February 25, 2002Publication date: October 3, 2002Applicant: Hitachi, Ltd.Inventors: Naoki Yada, Eiichi Ishikawa
-
Patent number: 6407959Abstract: A microcomputer incorporating a flash memory which is erased and programmed electrically in a stable manner within a relatively wide range of external power supply voltages including those for low-voltage operations. The microcomputer comprises a voltage clamp unit including a reference voltage generating circuit and a constant voltage generating circuit. In operation, the voltage clamp unit generates a voltage of a low dependency on a supply voltage and clamps the generated voltage to a voltage level which, within a tolerable range, is lower than a single supply voltage externally furnished. This prevents voltages boosted by boosting circuits operating on the clamped voltage, i.e., programming and erasure voltages, from being dependent on the externally supplied voltage.Type: GrantFiled: June 6, 2001Date of Patent: June 18, 2002Assignee: Hitachi, Ltd.Inventors: Eiichi Ishikawa, Yasuyuki Saito, Masanao Sato, Naoki Yada, Kiyoshi Matsubara
-
Publication number: 20020032891Abstract: The present invention provides a data processing system wherein the waste of use of each storage area by ECC codes is avoided to improve or increase the number of assurances for rewriting of information stored in a non-volatile memory.Type: ApplicationFiled: August 27, 2001Publication date: March 14, 2002Applicant: Hitachi, Ltd.Inventors: Naoki Yada, Eiichi Ishikawa, Mitsuru Hiraki, Shoji Shukuri