Patents by Inventor Eiji Fujii

Eiji Fujii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6174822
    Abstract: A semiconductor device includes: a capacitor provided on a supporting substrate having an integrated circuit thereon and including a lower electrode, a dielectric film, and an upper electrode; a first interlayer insulating film provided so as to cover the capacitor; a first interconnect selectively provided on the first interlayer insulating film and electrically connected to the integrated circuit and the capacitor through a first contact hole formed in the first interlayer insulating film; a second interlayer insulating film formed of ozone TEOS and provided so as to cover the first interconnect; a second interconnect selectively provided on the second interlayer insulating film and electrically connected to the first interconnect through a second contact hole formed in the second interlayer insulating film; and a passivation layer provided so as to cover the second interconnect.
    Type: Grant
    Filed: October 20, 1998
    Date of Patent: January 16, 2001
    Assignee: Matsushita Electronics Corporation
    Inventors: Yoshihisa Nagano, Toshie Kutsunai, Yuji Judai, Yasuhiro Uemoto, Eiji Fujii
  • Patent number: 6169304
    Abstract: A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm3 or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 1021 atoms/cm3 or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.
    Type: Grant
    Filed: May 4, 1998
    Date of Patent: January 2, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Koji Arita, Eiji Fujii, Yasuhiro Shimada, Yasuhiro Uemoto, Toru Nasu, Akihiro Matsuda, Yoshihisa Nagano, Atsuo Inoue, Taketoshi Matsuura, Tatsuo Otsuki
  • Patent number: 6126752
    Abstract: A semiconductor device comprising an integrated circuit and a capacitor. In this capacitor, a bottom electrode, a dielectric film and a top electrode are formed, independently of the integrated circuit, on the interlayer insulating film, and the top electrode and bottom electrode are connected with metal interconnections through contact holes opened in the protective film for protecting the surface of the capacitor. In this constitution, either the top electrode or the bottom electrode is connected the bias line of the integrated circuit, and the other is connected to the ground line, so that extraneous emission may be reduced without having to connect the capacitor outside.
    Type: Grant
    Filed: October 9, 1997
    Date of Patent: October 3, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Eiji Fujii, Yasuhiro Shimada, Yasuhiro Uemoto, Shinitirou Hayashi, Tooru Nasu, Koichi Arita, Atsuo Inoue, Akihiro Matsuda, Masaki Kibe, Tatsuo Ootsuki
  • Patent number: 6107657
    Abstract: A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm.sup.3 or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 10.sup.21 atoms/cm.sup.3 or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.
    Type: Grant
    Filed: May 4, 1998
    Date of Patent: August 22, 2000
    Assignee: Matsushita Electronics Corporation
    Inventors: Koji Arita, Eiji Fujii, Yasuhiro Shimada, Yasuhiro Uemoto, Toru Nasu, Akihiro Matsuda, Yoshihisa Nagano, Atsuo Inoue, Taketoshi Matsuura, Tatsuo Otsuki
  • Patent number: 6100100
    Abstract: The method of this invention provides a method for manufacturing a capacitor element composed of films. The films have a precise etched shape without a residue that may be generated as a reaction product in a dry-etching process. In this invention, washing in a non-oxidizing atmosphere, inclining a side of a mask for etching or heating a substrate prevents the reaction product from remaining on the film as a residue. The reaction product can be washed away with water, acid or organic solvent in inert gas. The reaction product can be removed from the side of the mask by sputter-etching with ions for dry-etching. The reaction product can be exhausted without adhering to the mask by heating the substrate at a temperature between 100.degree. C. and 400.degree. C.
    Type: Grant
    Filed: July 24, 1998
    Date of Patent: August 8, 2000
    Assignee: Matsushita Electronics Corporation
    Inventors: Yoshihisa Nagano, Yasuhiro Shimada, Eiji Fujii
  • Patent number: 6081182
    Abstract: The present invention provides a temperature sensor element having excellent heat resistance, quick heat response, stable resistance, and high reliability with a less variation in resistance against time. The temperature sensor element includes a thermo-sensitive film mainly composed of a heat sensitive material having electrical resistance varies depending on the temperature; a pair of electrode films arranged to measure the electrical resistance in the direction of the thickness of the thermo-sensitive film, a base plate mainly composed of a heat-resistant insulating material for supporting the thermo-sensitive film and the electrode films, an anti-diffusion film interposed between the thermo-sensitive film and the electrode film in the vicinity of the base plate, and a film mainly composed of a heat-resistant insulating material for covering the thermo-sensitive film and the electrode films except the lead-connecting terminals of the electrode films.
    Type: Grant
    Filed: November 14, 1997
    Date of Patent: June 27, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Atsushi Tomozawa, Eiji Fujii, Hideo Torii, Ryoichi Takayama
  • Patent number: 6080617
    Abstract: A semiconductor device comprising an integrated circuit and a capacitor. In this capacitor, a bottom electrode, a dielectric film and a top electrode are formed, independently of the integrated circuit, on the interlayer insulating film, and the top electrode and bottom electrode are connected with metal interconnections through contact holes opened in the protective film for protecting the surface of the capacitor. In this constitution, either the top electrode or the bottom electrode is connected the bias line of the integrated circuit, and the other is connected to the ground line, so that extraneous emission may be reduced without having to connect the capacitor outside.
    Type: Grant
    Filed: October 15, 1997
    Date of Patent: June 27, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Eiji Fujii, Yasuhiro Shimada, Yasuhiro Uemoto, Shinitirou Hayashi, Tooru Nasu, Koichi Arita, Atsuo Inoue, Akihiro Matsuda, Masaki Kibe, Tatsuo Ootsuki
  • Patent number: 6044795
    Abstract: An automatic feeding system includes a tag attached to a body of a pet; and an automatic feeding apparatus for automatically feeding the pet. The tag includes a receiving device for receiving an electromagnetic wave from the automatic feeding apparatus; an information memory device storing information on the feeding of the pet and outputting the information in response to an output from the receiving device; and a sending device for sending the information which is output from the information memory device to the automatic feeding apparatus using an electric wave.
    Type: Grant
    Filed: June 30, 1998
    Date of Patent: April 4, 2000
    Assignee: Matsushita Electronics Corporation
    Inventors: Taketoshi Matsuura, Eiji Fujii, Kazuhiro Mori
  • Patent number: 6046490
    Abstract: A semiconductor device is provided with a multilayered interconnection and a capacitor dielectric element, in which the transistor in the device has a non-degraded characteristics and the degradation of the capacitor dielectric element is suppressed. The semiconductor device has wiring layers connecting to one another through contact holes in insulating layers. One of the insulating layers is formed so as to cover at least a part of the area above the transistor and so as not to cover the area above the capacitor dielectric element. Hydrogen generated by heat-treating the insulating layer is supplied to the transistor to recover the damage in it, while hydrogen is suppressed from arriving at the capacitor element so that the capacitor dielectric element does not degrade.
    Type: Grant
    Filed: August 10, 1998
    Date of Patent: April 4, 2000
    Assignee: Matsushita Electronics Corporation
    Inventors: Koji Arita, Eiji Fujii, Yasuhiro Uemoto, Yoshihisa Nagano, Akihiro Matsuda
  • Patent number: 6046467
    Abstract: A capacitor 25 is formed on an insulating layer 21a formed on a semiconductor substrate 21. The end portion of a capacitor insulating layer 23 is positioned between the end portion of a bottom electrode 22 and the end portion of a top electrode 24. A passivation layer 26 for covering the capacitor 25 is formed. Interconnections 28 are connected to the bottom electrode 22 through a first hole 27a and to the top electrode 24 through a second hole 27b. In this way, since the end portion of the capacitor insulating layer 23 is out of the end portion of the top electrode 24, the end portion of the capacitor insulating layer 23 injured by etching does not affect the capacitance.
    Type: Grant
    Filed: June 20, 1996
    Date of Patent: April 4, 2000
    Assignee: Matsushita Electronics Corporation
    Inventors: Koji Arita, Akihiro Matsuda, Yoshihisa Nagano, Toru Nasu, Eiji Fujii
  • Patent number: 6015987
    Abstract: A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm.sup.3 or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 10.sup.21 atoms/cm.sup.3 or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.
    Type: Grant
    Filed: May 4, 1998
    Date of Patent: January 18, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Koji Arita, Eiji Fujii, Yasuhiro Shimada, Yasuhiro Uemoto, Toru Nasu, Akihiro Matsuda, Yoshihisa Nagano, Atsuo Inoue, Taketoshi Matsuura, Tatsuo Otsuki
  • Patent number: 6014073
    Abstract: A temperature sensor element for measuring the temperature of exhaust gas from car engines comprises a metallic support having a shape of a flat board, a first electric-insulating film existing on the support, a first temperature sensitive film existing on the first electric-insulating film and having a pair of electrodes, and a second electric-insulating film existing on the temperature sensitive film. The element is superior in thermal shock resistance. The element needs no heat-resistant cap. The element is superior in heat-response since the element has a small heat capacity.
    Type: Grant
    Filed: January 10, 1997
    Date of Patent: January 11, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hideo Torii, Takeshi Kamada, Atsushi Tomozawa, Eiji Fujii, Ryoichi Takayama, Hiroki Moriwake
  • Patent number: 5993543
    Abstract: The first object of the present invention is to provide a PDP with improved panel brightness which is achieved by improving the efficiency in conversion from discharge energy to visible rays. The second object of the present invention is to provide a PDP with improved panel life which is achieved by improving the protecting layer protecting the dielectrics glass layer. To achieve the first object, the present invention sets the amount of xenon in the discharge gas to the range of 10% by volume to less than 100% by volume, and sets the charging pressure for the discharge gas to the range of 500 to 760 Torr which is higher than conventional charging pressures. With such construction, the panel brightness increases. Also, to achieve the second object, the present invention has, on the surface of the dielectric glass layer, a protecting layer consisting of an alkaline earth oxide with (100)-face or (110)-face orientation.
    Type: Grant
    Filed: July 9, 1997
    Date of Patent: November 30, 1999
    Assignee: Masaki Aoki Et Al.
    Inventors: Masaki Aoki, Hideo Torii, Eiji Fujii, Mitsuhiro Ohtani, Takashi Inami, Hiroyuki Kawamura, Hiroyoshi Tanaka, Ryuichi Murai, Yasuhisa Ishikura, Yutaka Nishimura, Katsuyoshi Yamashita
  • Patent number: 5989395
    Abstract: A ferroelectric thin film includes lead titanate including La and at least an element which forms a six-coordinate bond with oxygen atoms and which is selected from the group consisting of Mg and Mn. The ferroelectric thin film is imparted with a high c-axis orientation while the film is formed without a polarization process. The ferroelectric thin film is manufactured by the steps of: positioning a MgO single crystal substrate disposed in advance with a foundation platinum electrode by a sputtering method on the surface of a substrate heater, exhausting a chamber, heating the substrate by a substrate heater, letting in sputtering gases Ar and O.sub.2 through a nozzle into the chamber, and maintaining a high degree of vacuum. Then, high frequency electric power is input to a target from a high frequency electric power source to generate plasma, and a film is formed on the substrate. In this way, a ferroelectric thin film containing, for example, [(1-x).Pb.sub.1-y La.sub.y Ti.sub.1-y/4 O.sub.3 +x.
    Type: Grant
    Filed: October 11, 1996
    Date of Patent: November 23, 1999
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Atsushi Tomozawa, Satoru Fujii, Eiji Fujii, Ryoichi Takayama, Masafumi Kobune, Satoshi Fujii
  • Patent number: 5943568
    Abstract: A method of making a semiconductor device include forming: (a) a semiconductor substrate on whose surface an integrated circuit is formed, (b) a first insulating layer on the semiconductor device and having first contact holes which lead to the integrated circuit, (c) a capacitance element on the first insulating layer, (d) a second insulating layer on the first insulating layer to cover the capacitance element, and having second contact holes which lead to an upper and a lower electrodes of the capacitance element respectively, and (e) interconnections which are connected to the integrated circuit and the capacitance element respectively through the first and second contact holes. The hydrogen density of this semiconductor device is 10.sup.11 atoms/cm.sup.2 or less.
    Type: Grant
    Filed: March 5, 1997
    Date of Patent: August 24, 1999
    Assignee: Matsushita Electronics Corporation
    Inventors: Eiji Fujii, Atsuo Inoue, Koji Arita, Toru Nasu, Akihiro Matsuda
  • Patent number: 5920574
    Abstract: A method for an accelerated test of semiconductor devices comprises the steps of determining a relational expression t.sub.1 =t.sub.2.sup.m between an information holding lifetime t.sub.1 at a temperature T.sub.1 and another lifetime t.sub.2 at another temperature T.sub.2, expressing the exponent m as a function of the temperature that is proportional to the Boltzmann's factor, and calculating the information holding lifetime t.sub.2 at the temperature T.sub.2 on the basis of the information holding lifetime t.sub.1 at the temperature T.sub.1 using the relational expression.
    Type: Grant
    Filed: September 18, 1997
    Date of Patent: July 6, 1999
    Assignee: Matsushita Electronics Corporation
    Inventors: Yasuhiro Shimada, Keisaku Nakao, Atsuo Inoue, Masamichi Azuma, Eiji Fujii
  • Patent number: 5866238
    Abstract: A first ferroelectric thin film device is provided with a first substrate consisting of polycrystal, amorphous material or metal material and a first ferroelectric thin film formed on the first substrate. The average of thermal expansion coefficients of the substrate from room temperature to temperature for forming the ferroelectric thin film is 70.times.10.sup.-7 /.degree.C. or more. At least 75% of crystal axes of the first ferroelectric thin film are oriented in <001>-direction. A second ferroelectric thin film device is provided with a second substrate consisting of amorphous material and a second ferroelectric thin film formed on the second substrate. The average of thermal expansion coefficients of the substrate from room temperature to temperature for forming the ferroelectric thin film is 50.times.10.sup.-7 /.degree.C. or less. At least 75% of crystal axes of the second ferroelectric thin film are oriented in <100>direction.
    Type: Grant
    Filed: March 4, 1997
    Date of Patent: February 2, 1999
    Assignee: Minolta Co., Ltd.
    Inventors: Ryoichi Takayama, Yoshihiro Tomita, Satoru Fujii, Masayuki Okano, Hideo Torii, Eiji Fujii, Atsushi Tomozawa
  • Patent number: 5795794
    Abstract: The present invention relates to method of manufacturing semiconductor devices having built-in capacitor comprising a dielectric substance of high dielectric constant or a ferroelectric substance as the capacitance insulation film, and aims to solve a problem that the prior art capacitance insulation film contained in semiconductor devices has a rough surface which results in a poor insulating voltage and a large spread in electrical characteristics, as well as broken connection wire; in which method a capacitance insulation film is produced by first forming a first dielectric film, and forming a second dielectric film on the first dielectric film for a thickness greater than the difference in level between top and bottom of the surface of first dielectric film, and forming a thin film whose etching speed is identical with that of the second dielectric film on the second dielectric film making the surface of thin film flat, and then etching the whole of the thin film and part of the second dielectric film off
    Type: Grant
    Filed: July 11, 1996
    Date of Patent: August 18, 1998
    Assignee: Matsushita Electronics Corporation
    Inventors: Yoshihisa Nagano, Eiji Fujii, Toru Nasu, Akihiro Matsuda
  • Patent number: 5780351
    Abstract: A semi conductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm.sup.3 or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 10.sup.21 atoms/cm.sup.3 or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.
    Type: Grant
    Filed: April 28, 1997
    Date of Patent: July 14, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Koji Arita, Eiji Fujii, Yasuhiro Shimada, Yasuhiro Uemoto, Toru Nasu, Akihiro Matsuda, Yoshihisa Nagano, Atsuo Inoue, Taketoshi Matsuura, Tatsuo Otsuki
  • Patent number: 5770921
    Abstract: The first object of the present invention is to provide a PDP with improved panel brightness which is achieved by improving the efficiency in conversion from discharge energy to visible rays. The second object of the present invention is to provide a PDP with improved panel life which is achieved by improving the protecting layer protecting the dielectrics glass layer. To achieve the first object, the present invention sets the amount of xenon in the discharge gas to the range of 10% by volume to less than 100% by volume, and sets the charging pressure for the discharge gas to the range of 500 to 760Torr which is higher than conventional charging pressures. With such construction, the panel brightness increases. Also, to achieve the second object, the present invention has, on the surface of the dielectrics glass layer, a protecting layer consisting of an alkaline earth oxide with (100)-face or (110)-face orientation.
    Type: Grant
    Filed: December 16, 1996
    Date of Patent: June 23, 1998
    Assignee: Matsushita Electric Co., Ltd.
    Inventors: Masaki Aoki, Hideo Torii, Eiji Fujii, Mitsuhiro Ohtani, Takashi Inami, Hiroyuki Kawamura, Hiroyoshi Tanaka, Ryuichi Murai, Yasuhisa Ishikura, Yutaka Nishimura, Katsuyoshi Yamashita