Patents by Inventor Eiji Kitagawa

Eiji Kitagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200012956
    Abstract: An action selection learning device includes a memory; and a processor coupled to the memory and configured to generate a reference model that is a set of model parameter vectors that indicate an influence level of each factor that influences selection of an action alternative, calculate a selection probability for each action alternative, for each of the model parameter vectors, calculate a model parameter vector for each user using a subset of model parameter vectors extracted from the reference model, based on the selection probability for each action alternative and a selection history of the action alternative by each user, generate the action alternatives based on the model parameter vector for each user, and transmit the generated action alternatives to a terminal device.
    Type: Application
    Filed: September 19, 2019
    Publication date: January 9, 2020
    Applicant: FUJITSU LIMITED
    Inventors: Takuro Ikeda, Taizo ANAN, Eiji Kitagawa, Vishal Sharma
  • Publication number: 20190173001
    Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a first magnetic layer; a second magnetic layer; and a spacer layer interposed between the first magnetic layer and the second magnetic layer, wherein the spacer layer includes a first layer, a second layer and an intermediate layer interposed between the first layer and the second layer, and wherein each of the first layer and the second layer includes an oxide, or a nitride, or a combination of an oxide and a nitride, the intermediate layer includes a multilayer structure including [Ru/x]n or [x/Ru]n, x includes a metal, an oxide, or a nitride, or a combination of a metal, an oxide and a nitride, and n represents an integer of 1 or greater.
    Type: Application
    Filed: December 4, 2018
    Publication date: June 6, 2019
    Inventors: Tae-Young LEE, Jae-Hyoung LEE, Sung-Woong CHUNG, Eiji KITAGAWA
  • Patent number: 10269866
    Abstract: A magnetoresistive element includes: a first ferromagnetic layer; a second ferromagnetic layer; and a first nonmagnetic layer disposed between the first ferromagnetic layer and the second ferromagnetic layer, the first ferromagnetic layer including (MnxGay)100-zPtz, the (MnxGay)100-zPtz having a tetragonal crystal structure, where 45 atm %?x?75 atm %, 25 atm %?y?55 atm %, x+y=100 atm %, and 0 atm %<z?7 atm %.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: April 23, 2019
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOHOKU UNIVERSITY
    Inventors: Yushi Kato, Tadaomi Daibou, Eiji Kitagawa, Takao Ochiai, Junichi Ito, Takahide Kubota, Shigemi Mizukami, Terunobu Miyazaki
  • Publication number: 20190081235
    Abstract: According to one embodiment, a semiconductor memory device includes a variable resistance element comprising a first ferromagnetic layer, a second ferromagnetic layer, and a non-magnetic layer between the first ferromagnetic layer and the second ferromagnetic layer. The non-magnetic layer includes a para-electric layer on an upper surface of the first ferromagnetic layer, and a ferro-electric layer on an upper surface of the para-electric layer and on a lower surface of the second ferromagnetic layer.
    Type: Application
    Filed: February 28, 2018
    Publication date: March 14, 2019
    Inventor: Eiji KITAGAWA
  • Patent number: 10211256
    Abstract: According to one embodiment, a magnetic memory device includes a stack structure including a first magnetic layer having a variable magnetization direction, a second magnetic layer having a fixed magnetization direction, and a nonmagnetic layer provided between the first magnetic layer and the second magnetic layer, wherein the second magnetic layer includes a first layer containing iron (Fe) and boron (B), a second layer containing iron (Fe) and boron (B), and a third layer provided between the first layer and the second layer and containing a semiconductor.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: February 19, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Eiji Kitagawa
  • Publication number: 20190019404
    Abstract: A congestion management apparatus includes a memory configured to store, on a per-action-option basis, upper limits on numbers of users allowed to be guided to action options, and a processor coupled to the memory and configured to: generate the action options by time slot for a user; calculate for each of the generated action options, choice probabilities of the action options with respect to the user, and store the calculated choice probabilities in the memory; and calculate for each of the action options, estimated numbers of previous users assumed to have selected the action options, based on choice probabilities of each of the action options with respect to the previous users, the choice probabilities being obtained from the memory, wherein the processor is configured to extract, based on the upper limits and the estimated numbers for the action options, action options to be presented to the user.
    Type: Application
    Filed: September 19, 2018
    Publication date: January 17, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Takuro IKEDA, Eiji KITAGAWA, Vishal SHARMA
  • Publication number: 20180309048
    Abstract: A magnetoresistive effect element including a substrate; a pinned layer above the substrate; a free layer between the substrate and the pinned layer; a non-magnetic layer between the free layer and the pinned layer; a first layer provided on an opposite side of a side of the non-magnetic layer of the free layer, the first layer being between the substrate and the free layer, the first layer being in direct contact with the free layer, the first layer being non-magnetic and the first layer including a MgFeO layer, the MgFeO layer being an amorphous layer and being in direct contact with the free layer; and a second layer between the first layer and the substrate, the second layer being in contact with the substrate.
    Type: Application
    Filed: June 19, 2018
    Publication date: October 25, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Takao Ochiai, Eiji Kitagawa, Kenji Noma
  • Patent number: 10026888
    Abstract: According to one embodiment, a magnetoresistive effect element includes: a first magnetic layer; a second magnetic layer; a non-magnetic film between the first magnetic layer and the second magnetic layer; a first layer on an opposite side of a side of the non-magnetic layer of the first magnetic layer, the first layer including magnesium oxide as a principal component; and a second layer between the first film and the first magnetic layer, the second layer including a material different from a material of the first layer.
    Type: Grant
    Filed: March 5, 2015
    Date of Patent: July 17, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takao Ochiai, Eiji Kitagawa, Kenji Noma
  • Patent number: 9831420
    Abstract: A magnetoresistive element according to an embodiment includes: a first layer containing nitrogen; a reference layer opposed to the first layer, the reference layer having a magnetization perpendicular to a face thereof opposed to the first layer, the magnetization of the reference layer being fixed; a storage layer disposed between the first layer and the reference layer, the storage layer having a magnetization perpendicular to a face thereof opposed to the first layer, the magnetization of the storage layer being changeable, and the storage layer including a second layer containing boron, and a third layer disposed between the second layer and the reference layer and containing boron, a boron concentration of the third layer being lower than a boron concentration of the second layer; and an intermediate layer disposed between the third layer and the reference.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: November 28, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Eiji Kitagawa, Takao Ochiai
  • Patent number: 9780298
    Abstract: According to one embodiment, a magnetoresistive element includes a recording layer having a variable magnetization direction, a reference layer having an invariable magnetization direction, an intermediate layer provided between the recording layer and the reference layer, and a first buffer layer provided on a surface of the recording layer, which is opposite to a surface of the recording layer where the intermediate layer is provided. The recording layer comprises a first magnetic layer which is provided in a side of the intermediate layer and contains CoFe as a main component, and a second magnetic layer which is provided in a side of the first buffer layer and contains CoFe as a main component, a concentration of Fe in the first magnetic layer being higher than a concentration of Fe in the second magnetic layer. The first buffer layer comprises a nitrogen compound.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: October 3, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Eiji Kitagawa, Tadaomi Daibou, Tadashi Kai, Toshihiko Nagase, Kenji Noma, Hiroaki Yoda
  • Publication number: 20170263679
    Abstract: According to one embodiment, a magnetic memory device includes a first magnetic layer having a variable magnetization direction, and including a first main surface and a second main surface located opposite to the first main surface, a second magnetic layer provided on a first main surface side of the first magnetic layer, and having a fixed magnetization direction, and a nonmagnetic layer provided between the first magnetic layer and the second magnetic layer, wherein saturation magnetization of part of the first magnetic layer which is located close to the first main surface is higher than saturation magnetization of part of the first magnetic layer which is located close to the second main surface.
    Type: Application
    Filed: September 16, 2016
    Publication date: September 14, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Jyunichi OZEKI, Masahiko NAKAYAMA, Hiroaki YODA, Eiji KITAGAWA, Takao OCHIAI, Minoru AMANO, Kenji NOMA
  • Publication number: 20170263678
    Abstract: According to one embodiment, a magnetic memory device includes a stacked structure which comprises a first magnetic layer having a variable magnetization direction, a second magnetic layer, and a nonmagnetic layer provided between the first magnetic layer and the second magnetic layer, and is allowed to be selectively set to a low-resistance state and a high-resistance state having a resistance greater than that of the low-resistance state based on a magnetization direction of the first magnetic layer, the high-resistance state being stable in a stationary state where no current flows through the stacked structure, and a magnetic field supply unit which supplies, to the first magnetic layer, a magnetic field having a direction opposite to a direction of a vertical magnetic field component of a total magnetic field applied from the second magnetic layer to the first magnetic layer.
    Type: Application
    Filed: September 16, 2016
    Publication date: September 14, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Eiji KITAGAWA
  • Patent number: 9647203
    Abstract: According to one embodiment, a magnetoresistive element includes a first magnetic layer including O and one of Co, Fe, Ni and Mn, a second magnetic layer, a nonmagnetic layer between the first and second magnetic layers, a first electrode connected to the first magnetic layer, a second electrode connected to the second magnetic layer, and a resistive layer including N between the first magnetic layer and the first electrode.
    Type: Grant
    Filed: July 16, 2014
    Date of Patent: May 9, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Eiji Kitagawa, Minoru Amano
  • Patent number: 9640752
    Abstract: According to one embodiment, a magnetoresistive element includes a recording layer having magnetic anisotropy perpendicular to a film surface and having a variable magnetization direction, a reference layer having magnetic anisotropy perpendicular to a film surface and having an invariable magnetization direction, an intermediate layer provided between the recording layer and the reference layer, and a underlayer containing AlTiN and provided on an opposite side of a surface of the recording layer on which the intermediate layer is provided.
    Type: Grant
    Filed: September 21, 2015
    Date of Patent: May 2, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Eiji Kitagawa, Tadashi Kai, Hiroaki Yoda
  • Patent number: 9620189
    Abstract: A magnetic memory according to an embodiment includes at least one MTJ element, the MTJ element including: a magnetic multilayer structure including a first magnetic layer in which a direction of magnetization is fixed, a second magnetic layer in which a direction of magnetization is changeable, and a tunnel barrier layer located between the first and second magnetic layers; a first electrode provided on a first surface of the magnetic multilayer structure; a second electrode provided on a second surface of the magnetic multilayer structure; an insulating film provided on a side surface of the magnetic multilayer structure; and a control electrode provided on the side surface of the magnetic multilayer structure with the insulating film located therebetween, a voltage being applied to the control electrode in a read operation, which increases an energy barrier for changing the magnetization of the second magnetic layer.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: April 11, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Naoharu Shimomura, Eiji Kitagawa, Minoru Amano, Daisuke Saida, Kay Yakushiji, Takayuki Nozaki, Shinji Yuasa, Akio Fukushima, Hiroshi Imamura, Hitoshi Kubota
  • Patent number: 9608199
    Abstract: According to one embodiment, a magnetic memory device includes a stack structure including a first magnetic layer variable in magnetization direction, a second magnetic layer fixed in magnetization direction, and a nonmagnetic layer between the first magnetic layer and the second magnetic layer, the first magnetic layer including a first layer, a second layer, and a third layer between the first layer and the second layer and containing magnesium (Mg), iron (Fe), and oxygen (O), the second layer being between the nonmagnetic layer and the third layer, wherein a thickness of the second layer is greater than that of the first layer, and the thickness of the first layer is greater than that of the third layer.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: March 28, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Eiji Kitagawa
  • Publication number: 20170077176
    Abstract: According to one embodiment, a magnetic memory device includes a stack structure including a first magnetic layer having a variable magnetization direction, a second magnetic layer having a fixed magnetization direction, and a nonmagnetic layer provided between the first magnetic layer and the second magnetic layer, wherein the second magnetic layer includes a first layer containing iron (Fe) and boron (B), a second layer containing iron (Fe) and boron (B), and a third layer provided between the first layer and the second layer and containing a semiconductor.
    Type: Application
    Filed: March 14, 2016
    Publication date: March 16, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Eiji KITAGAWA
  • Publication number: 20170069833
    Abstract: According to one embodiment, a magnetic memory device includes a stack structure including a first magnetic layer variable in magnetization direction, a second magnetic layer fixed in magnetization direction, and a nonmagnetic layer between the first magnetic layer and the second magnetic layer, the first magnetic layer including a first layer, a second layer, and a third layer between the first layer and the second layer and containing magnesium (Mg), iron (Fe), and oxygen (O), the second layer being between the nonmagnetic layer and the third layer, wherein a thickness of the second layer is greater than that of the first layer, and the thickness of the first layer is greater than that of the third layer.
    Type: Application
    Filed: March 14, 2016
    Publication date: March 9, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Eiji KITAGAWA
  • Patent number: 9508926
    Abstract: A magnetoresistive effect element includes a recording layer having magnetic anisotropy and a variable magnetization direction, a reference layer having magnetic anisotropy and an invariable magnetization direction, an intermediate layer between the recording layer and the reference layer, an underlayer containing scandium (Sc) and disposed on a surface side of the recording layer opposite to a surface side on which the recording layer is disposed, and a side wall layer containing an oxide of Sc and disposed on side surfaces of the recording layer and the intermediate layer.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: November 29, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Eiji Kitagawa, Minoru Amano, Megumi Yakabe, Hiroaki Maekawa
  • Patent number: 9466350
    Abstract: According to one embodiment, a magnetic memory device includes a first interconnect, a second interconnect, a magnetoresistive effect element having first and second terminals, the first terminal being electrically connected to the first interconnect, a diode having first and second terminals, the first terminal being electrically connected to the first terminal of the magnetoresistive effect element, the second terminal being electrically connected to the second terminal of the magnetoresistive effect element, and a transistor having source and drain terminals, one of the source and drain terminals being electrically connected to the second terminal of the magnetoresistive effect element and the second terminal of the diode, the other of the source and drain terminals being electrically connected to the second interconnect.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: October 11, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Akiyuki Murayama, Eiji Kitagawa, Masahiko Nakayama, Minoru Amano, Takao Ochiai