Patents by Inventor Eiji Makino

Eiji Makino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9628729
    Abstract: An image sensor that has a pixel array section in which pixels are arrayed in a two-dimensional manner in vertical and horizontal directions and that controls an exposure time of each pixel in a rolling shutter method is disclosed. The sensor includes control means for determining an electronic shutter occurrence number within one horizontal scanning period, which is the number of rows where electronic shutters are simultaneously performed in one horizontal scanning period, by an operation based on an address addition amount (P1, P2, P3, . . . , PN) when a vertical address movement amount of the pixel array section for every one horizontal scanning period in an exposure regulation shutter, which is an electronic shutter for regulating exposure, executed corresponding to electric charge reading in each pixel is expressed as repetition of the address addition amount (P1, P2, P3, . . . , PN).
    Type: Grant
    Filed: February 2, 2015
    Date of Patent: April 18, 2017
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Eiji Makino, Takahiro Abiru, Ryoji Suzuki, Masahiro Itoh
  • Patent number: 9490291
    Abstract: A MOS type solid state imaging device in which unit pixels, each having a photodiode, a transfer transistor for transferring the signal of the photodiode to a floating node, an amplifier transistor for outputting the signal of the floating node to a vertical signal line, and a reset transistor for resetting the floating node are arrayed in a matrix. A gate voltage of the reset transistor is controlled by three values of a power source potential (for example 3V), a ground potential (0V), and a negative power source potential (for example ?1V).
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: November 8, 2016
    Assignee: SONY CORPORATION
    Inventors: Tetsuo Nomoto, Eiji Makino, Keiji Mabuchi, Tsutomu Haruta, Shinjiro Kameda
  • Patent number: 9363453
    Abstract: A solid-state imaging device includes: a pixel section wherein pixels including photoelectric conversion devices are arranged in a matrix; and a pixel driving section including a row selection circuit which controls the pixels to perform an electronic shutter operation and readout of the pixel section. The row selection circuit has a function of selecting a readout row from which a signal is read out and a shutter row on which reset is performed by discharging charge accumulated in the photoelectric conversion devices, in accordance with address and control signals. The row selection circuit can set, in accordance with the address and control signals, in the pixels of the selected row, at least a readout state, a discharge state where a smaller amount of the charge accumulated in the photoelectric conversion devices than the reset is discharged, an electronic shutter state, and a charge state where the charge is accumulated in the photoelectric conversion devices.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: June 7, 2016
    Assignee: SONY CORPORATION
    Inventors: Eiji Makino, Tetsuji Nakaseko, Ryoji Eki, Youji Sakioka
  • Publication number: 20150334270
    Abstract: A MOS type solid state imaging device in which unit pixels, each having a photodiode, a transfer transistor for transferring the signal of the photodiode to a floating node, an amplifier transistor for outputting the signal of the floating node to a vertical signal line, and a reset transistor for resetting the floating node are arrayed in a matrix. A gate voltage of the reset transistor is controlled by three values of a power source potential (for example 3V), a ground potential (0V), and a negative power source potential (for example ?1V).
    Type: Application
    Filed: June 23, 2015
    Publication date: November 19, 2015
    Inventors: Tetsuo Nomoto, Eiji Makino, Keiji Mabuchi, Tsutomu Haruta, Shinjiro Kameda
  • Patent number: 9129879
    Abstract: An MOS type solid state imaging device in which unit pixels 10 each having a photodiode 11, a transfer transistor 12 for transferring the signal of the photodiode 11 to a floating node N11, an amplifier transistor 13 for outputting the signal of the floating node N11 to a vertical signal line 22, and a reset transistor 14 for resetting the floating node N11 are arrayed in a matrix and in which a gate voltage of the reset transistor 14 is controlled by three values of a power source potential (for example 3V), a ground potential (0V), and a negative power source potential (for example ?1V).
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: September 8, 2015
    Assignee: SONY CORPORATION
    Inventors: Tetsuo Nomoto, Eiji Makino, Keiji Mabuchi, Tsutomu Haruta, Shinjiro Kameda
  • Publication number: 20150249798
    Abstract: An MOS type solid state imaging device in which unit pixels 10 each having a photodiode 11, a transfer transistor 12 for transferring the signal of the photodiode 11 to a floating node N11, an amplifier transistor 13 for outputting the signal of the floating node N11 to a vertical signal line 22, and a reset transistor 14 for resetting the floating node N11 are arrayed in a matrix and in which a gate voltage of the reset transistor 14 is controlled by three values of a power source potential (for example 3V), a ground potential (OV), and a negative power source potential (for example ?1V).
    Type: Application
    Filed: February 26, 2015
    Publication date: September 3, 2015
    Inventors: Tetsuo Nomoto, Eiji Makino, Keiji Mabuchi, Tsutomu Haruta, Shinjiro Kameda
  • Patent number: 9112355
    Abstract: A power supply device that switches one of a first power supply, a second power supply, and a third power supply, all of which supply power to an auxiliary device, to a transfer gate in a CMOS image sensor having a photodiode and outputs the corresponding power to the transfer gate is disclosed. The device includes: a first transistor driven by the second power supply and outputting power of the second power supply to the transfer gate; a second transistor driven by the second power supply and outputting power of the first power supply to the transfer gate; a third transistor driven by the third power supply and outputting power of the third power supply to the transfer gate; and a fourth transistor located before the second transistor, driven by the first power supply, and outputting power of the first power supply to a source of the second transistor.
    Type: Grant
    Filed: April 2, 2014
    Date of Patent: August 18, 2015
    Assignee: Sony Corporation
    Inventors: Eiji Makino, Youji Sakioka, Shizunorl Matsumoto
  • Publication number: 20150146059
    Abstract: An image sensor that has a pixel array section in which pixels are arrayed in a two-dimensional manner in vertical and horizontal directions and that controls an exposure time of each pixel in a rolling shutter method is disclosed. The sensor includes control means for determining an electronic shutter occurrence number within one horizontal scanning period, which is the number of rows where electronic shutters are simultaneously performed in one horizontal scanning period, by an operation based on an address addition amount (P1, P2, P3, . . . , PN) when a vertical address movement amount of the pixel array section for every one horizontal scanning period in an exposure regulation shutter, which is an electronic shutter for regulating exposure, executed corresponding to electric charge reading in each pixel is expressed as repetition of the address addition amount (P1, P2, P3, . . . , PN).
    Type: Application
    Filed: February 2, 2015
    Publication date: May 28, 2015
    Inventors: Eiji Makino, Takahiro Abiru, Ryoji Suzuki, Masahiro Itoh
  • Publication number: 20150109502
    Abstract: A solid-state imaging device includes: a pixel section wherein pixels including photoelectric conversion devices are arranged in a matrix; and a pixel driving section including a row selection circuit which controls the pixels to perform an electronic shutter operation and readout of the pixel section. The row selection circuit has a function of selecting a readout row from which a signal is read out and a shutter row on which reset is performed by discharging charge accumulated in the photoelectric conversion devices, in accordance with address and control signals. The row selection circuit can set, in accordance with the address and control signals, in the pixels of the selected row, at least a readout state, a discharge state where a smaller amount of the charge accumulated in the photoelectric conversion devices than the reset is discharged, an electronic shutter state, and a charge state where the charge is accumulated in the photoelectric conversion devices.
    Type: Application
    Filed: December 30, 2014
    Publication date: April 23, 2015
    Inventors: Eiji Makino, Tetsuji Nakaseko, Ryoji Eki, Youji Sakioka
  • Patent number: 9001244
    Abstract: An image sensor that has a pixel array section in which pixels are arrayed in a two-dimensional manner in vertical and horizontal directions and that controls an exposure time of each pixel in a rolling shutter method is disclosed. The sensor includes control means for determining an electronic shutter occurrence number within one horizontal scanning period, which is the number of rows where electronic shutters are simultaneously performed in one horizontal scanning period, by an operation based on an address addition amount (P1, P2, P3, . . . , PN) when a vertical address movement amount of the pixel array section for every one horizontal scanning period in an exposure regulation shutter, which is an electronic shutter for regulating exposure, executed corresponding to electric charge reading in each pixel is expressed as repetition of the address addition amount (P1, P2, P3, . . . , PN).
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: April 7, 2015
    Assignee: Sony Corporation
    Inventors: Eiji Makino, Takahiro Abiru, Ryoji Suzuki, Masahiro Itoh
  • Patent number: 8970753
    Abstract: A solid-state imaging device includes: a pixel section wherein pixels including photoelectric conversion devices are arranged in a matrix; and a pixel driving section including a row selection circuit which controls the pixels to perform an electronic shutter operation and readout of the pixel section. The row selection circuit has a function of selecting a readout row from which a signal is read out and a shutter row on which reset is performed by discharging charge accumulated in the photoelectric conversion devices, in accordance with address and control signals. The row selection circuit can set, in accordance with the address and control signals, in the pixels of the selected row, at least a readout state, a discharge state where a smaller amount of the charge accumulated in the photoelectric conversion devices than the reset is discharged, an electronic shutter state, and a charge state where the charge is accumulated in the photoelectric conversion devices.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: March 3, 2015
    Assignee: Sony Corporation
    Inventors: Eiji Makino, Tetsuji Nakaseko, Ryoji Eki, Youji Sakioka
  • Publication number: 20140210274
    Abstract: A power supply device that switches one of a first power supply, a second power supply, and a third power supply, all of which supply power to an auxiliary device, to a transfer gate in a CMOS image sensor having a photodiode and outputs the corresponding power to the transfer gate is disclosed. The device includes: a first transistor driven by the second power supply and outputting power of the second power supply to the transfer gate; a second transistor driven by the second power supply and outputting power of the first power supply to the transfer gate; a third transistor driven by the third power supply and outputting power of the third power supply to the transfer gate; and a fourth transistor located before the second transistor, driven by the first power supply, and outputting power of the first power supply to a source of the second transistor.
    Type: Application
    Filed: April 2, 2014
    Publication date: July 31, 2014
    Applicant: Sony Corporation
    Inventors: Eiji MAKINO, Youji SAKIOKA, ShizunorI MATSUMOTO
  • Publication number: 20140204254
    Abstract: An image sensor that has a pixel array section in which pixels are arrayed in a two-dimensional manner in vertical and horizontal directions and that controls an exposure time of each pixel in a rolling shutter method is disclosed. The sensor includes control means for determining an electronic shutter occurrence number within one horizontal scanning period, which is the number of rows where electronic shutters are simultaneously performed in one horizontal scanning period, by an operation based on an address addition amount (P1, P2, P3, . . . , PN) when a vertical address movement amount of the pixel array section for every one horizontal scanning period in an exposure regulation shutter, which is an electronic shutter for regulating exposure, executed corresponding to electric charge reading in each pixel is expressed as repetition of the address addition amount (P1, P2, P3, . . . , PN).
    Type: Application
    Filed: March 19, 2014
    Publication date: July 24, 2014
    Applicant: Sony Corporation
    Inventors: Eiji Makino, Takahiro Abiru, Ryoji Suzuki, Masahiro Itoh
  • Patent number: 8767104
    Abstract: An image sensor that has a pixel array section in which pixels are arrayed in a two-dimensional manner in vertical and horizontal directions and that controls an exposure time of each pixel in a rolling shutter method is disclosed. The sensor includes control means for determining an electronic shutter occurrence number within one horizontal scanning period, which is the number of rows where electronic shutters are simultaneously performed in one horizontal scanning period, by an operation based on an address addition amount (P1, P2, P3, . . . , PN) when a vertical address movement amount of the pixel array section for every one horizontal scanning period in an exposure regulation shutter, which is an electronic shutter for regulating exposure, executed corresponding to electric charge reading in each pixel is expressed as repetition of the address addition amount (P1, P2, P3, . . . , PN).
    Type: Grant
    Filed: May 4, 2011
    Date of Patent: July 1, 2014
    Assignee: Sony Corporation
    Inventors: Eiji Makino, Takahiro Abiru, Ryoji Suzuki, Masahiro Itoh
  • Patent number: 8730355
    Abstract: An image signal processing device includes: a color mixture correction circuit correcting color mixture among pixels arranged in the row and column directions, having plural light receiving units which perform photoelectric conversion and including filters dividing light incident on respective plural light receiving units into plural color components, wherein the color mixture correction circuit performs correction processing to a signal value of a target pixel of color mixture correction by associating respective signal values of neighboring pixels adjacent to the target pixel of color mixture correction with correction parameters unique to an address of each signal.
    Type: Grant
    Filed: January 14, 2011
    Date of Patent: May 20, 2014
    Assignee: Sony Corporation
    Inventors: Ryoji Eki, Eiji Makino
  • Patent number: 8716895
    Abstract: A power supply device that switches one of a first power supply, a second power supply, and a third power supply, all of which supply power to an auxiliary device, to a transfer gate in a CMOS image sensor having a photodiode and outputs the corresponding power to the transfer gate is disclosed. The device includes: a first transistor driven by the second power supply and outputting power of the second power supply to the transfer gate; a second transistor driven by the second power supply and outputting power of the first power supply to the transfer gate; a third transistor driven by the third power supply and outputting power of the third power supply to the transfer gate; and a fourth transistor located before the second transistor, driven by the first power supply, and outputting power of the first power supply to a source of the second transistor.
    Type: Grant
    Filed: April 15, 2008
    Date of Patent: May 6, 2014
    Assignee: Sony Corporation
    Inventors: Eiji Makino, Youji Sakioka, Shizunori Matsumoto
  • Patent number: 8711260
    Abstract: An image sensor that has a pixel array section in which pixels are arrayed in a two-dimensional manner in vertical and horizontal directions and that controls an exposure time of each pixel in a rolling shutter method is disclosed. The sensor includes control means for determining an electronic shutter occurrence number within one horizontal scanning period, which is the number of rows where electronic shutters are simultaneously performed in one horizontal scanning period, by an operation based on an address addition amount (P1, P2, P3, . . . , PN) when a vertical address movement amount of the pixel array section for every one horizontal scanning period in an exposure regulation shutter, which is an electronic shutter for regulating exposure, executed corresponding to electric charge reading in each pixel is expressed as repetition of the address addition amount (P1, P2, P3, . . . , PN).
    Type: Grant
    Filed: May 4, 2011
    Date of Patent: April 29, 2014
    Assignee: Sony Corporation
    Inventors: Eiji Makino, Takahiro Abiru, Ryoji Suzuki, Masahiro Itoh
  • Patent number: 8692914
    Abstract: An image sensor includes a solid-state image pickup device, an optical system, and a flash. The solid-state image pickup device has an electronic shutter function of outputting accumulated signal charges at a timing corresponding to a shutter speed. The optical system collects incident light to an image pickup area of the solid-state image pickup device. The flash irradiates light to an object to be photographed by the solid-state image pickup device. The solid-state image pickup device includes a pulse generator circuit for generating one or more of an electronic shutter pulse for controlling an accumulation time of signal charges by using the electronic shutter function, an optical system movement pulse for controlling movement of the optical system, and a flash pulse for controlling an emission timing of the flash.
    Type: Grant
    Filed: May 14, 2008
    Date of Patent: April 8, 2014
    Assignee: Sony Corporation
    Inventors: Tsutomu Haruta, Eiji Makino, Takeshi Yamaguchi, Tatsuya Matsumura
  • Patent number: 8692899
    Abstract: A solid-state imaging device includes: an imaging unit taking a subject image focused by an imaging optical system; a digital signal processing unit generating image data of the subject image taken by the imaging unit and luminance data thereof; an input/output unit inputting and outputting data; a focus evaluation value generating unit generating a focus evaluation value of the subject image based on the luminance data outputted from the digital signal processing unit and outputting the focus evaluation value from the input/output unit; and an imaging drive unit starting an imaging operation by the imaging unit when an imaging instruction signal is inputted from the input/output unit, and outputting an imaging-end timing signal from the input/output unit when the imaging operation is completed.
    Type: Grant
    Filed: November 17, 2009
    Date of Patent: April 8, 2014
    Assignee: Sony Corporation
    Inventors: Tsutomu Haruta, Eiji Makino, Takeshi Yamaguchi, Shinsuke Shimomoto
  • Publication number: 20140022428
    Abstract: An MOS type solid state imaging device in which unit pixels 10 each having a photodiode 11, a transfer transistor 12 for transferring the signal of the photodiode 11 to a floating node N11, an amplifier transistor 13 for outputting the signal of the floating node N11 to a vertical signal line 22, and a reset transistor 14 for resetting the floating node N11 are arrayed in a matrix and in which a gate voltage of the reset transistor 14 is controlled by three values of a power source potential (for example 3V), a ground potential (0V), and a negative power source potential (for example ?1V).
    Type: Application
    Filed: September 24, 2013
    Publication date: January 23, 2014
    Applicant: Sony Corporation
    Inventors: Tetsuo Nomoto, Eiji Makino, Keiji Mabuchi