Abstract: The present invention relates to: a memory cell array which is capable of decreasing the parasitic capacitance or load capacitance of signal electrodes and has ferroelectric layers making up ferroelectric capacitors and having a predetermined pattern; a method of fabricating the memory cell array, and a ferroelectric memory device. In the memory cell array, memory cells formed of ferroelectric capacitors are arranged in a matrix. The ferroelectric capacitors include first signal electrodes, second signal electrodes arranged in a direction intersecting the first signal electrodes, and ferroelectric layers disposed linearly along either the first signal electrodes or the second signal electrodes. Alternatively, the ferroelectric layers may be disposed only in intersection areas of the first and second signal electrodes.

Abstract: A method of manufacturing a ceramic film includes a step of forming a ceramic film 30 by crystallizing a raw material body 20. The raw material body 20 contains different types of raw materials in a mixed state. The different types of raw materials differ from one another in at least one of a crystal growth condition and a crystal growth mechanism in the crystallization of the raw materials. According to this manufacturing method, a surface morphology of the ceramic film can be improved.

Abstract: The present invention is equipped with a ferroelectric film having concave and convex patterns formed on both sides thereof corresponding to respective electrodes of a plurality of capacitors. A first substrate has first electrodes of the plurality of capacitors formed on one surface thereof. A second substrate has second electrodes of the plurality of capacitors formed on the other surface thereof. First and second anisotropic conduction films are provided between one surface of the ferroelectric film and the first substrate and between the other surface of the ferroelectric film and the second electrode film, respectively, to thereby establish conduction between the convex sections of the ferroelectric film of the capacitors and the electrodes of the capacitors. Since the multiple capacitors can be formed without conducting an etching (lithography) process, damages that may be inflicted on the ferroelectric film when the ferroelectric capacitors are formed can be reduced.

Abstract: A method of manufacturing a ceramic includes forming a film which includes a complex oxide material having an oxygen octahedral structure and a paraelectric material having a catalytic effect for the complex oxide material in a mixed state, and performing a heat treatment to the film, wherein the paraelectric material is one of a layered catalytic substance which includes Si in the constituent elements and a layered catalytic substance which includes Si and Ge in the constituent elements. The heat treatment includes sintering and post-annealing. At least the post-annealing is performed in a pressurized atmosphere including at least one of oxygen and ozone. A ceramic is a complex oxide having an oxygen octahedral structure, and has Si and Ge in the oxygen octahedral structure.

Abstract: A method of manufacturing a ceramic film includes forming the ceramic film by crystallizing a ceramic raw material liquid which includes a first raw material liquid and a second raw material liquid. The first raw material liquid and the second raw material liquid are different types of liquids, the first raw material liquid is a raw material liquid for producing a ferroelectric, the second raw material liquid is a raw material liquid for producing an oxide such as an ABO-type oxide, a solvent included in the first raw material liquid and a solvent included in the second raw material liquid have different polarities, and the ceramic film is formed in a state in which the first raw material liquid and the second raw material liquid are phase separated so that first crystals formed of the first raw material liquid are intermittently formed in a surface direction of the ceramic film and second crystals formed of the second raw material liquid are formed so as to interpose between the first crystals.

Abstract: A ferroelectric memory device includes memory cells including ferroelectric capacitors formed in regions in which first signal electrodes intersect second signal electrodes. Information is written into a selected memory cell by applying a write voltage between one of the first signal electrodes and one of the second signal electrodes in the memory cell. Information is read from the selected memory cell by applying a read voltage between one of the first signal electrodes and one of the second signal electrodes in the memory cell. Provided that the write voltage is ±Vs and the read voltage is either +Vs or −Vs, |Vs| is less than the absolute value of a saturation voltage at which remanent polarization of the ferroelectric capacitors is saturated.

Abstract: A ferroelectric memory device includes a simple matrix type memory cell array. Provided that the maximum absolute value of a voltage applied between a first signal electrode and a second signal electrode is Vs, polarization P of a ferroelectric capacitor formed of the first electrode, the second electrode, and ferroelectric layer is within the range of 0.1 P(+Vs)<P(−⅓Vs) when the applied voltage is changed from +Vs to −⅓Vs, and 0.1 P(−Vs)>P(+⅓Vs) when the applied voltage is changed from −Vs to +⅓Vs.

Abstract: The present invention relates to a ferroelectric memory having a matrix-type memory cell array which has an excellent degree of integration, in which the angularity of the ferroelectric layer's hysteresis curve is improved. A ferroelectric memory having both integration and memory characteristics in which the angularity of the ferroelectric layer's hysteresis curve is improved is realized as follows. Namely, a structure is employed in which the memory cell array and the peripheral circuit are in a plane separated from one another, and the ferroelectric layer is made to undergo epitaxial growth on to a Si single crystal via a buffer and the first signal electrodes.

Abstract: The present invention relates to a ferroelectric memory having a matrix-type memory cell array which has a superior degree of integration, in which the angularity of the ferroelectric layer's hysteresis curve is improved, the production yield is increased and costs are reduced.

Abstract: A method for manufacturing ceramics includes a step of forming a ceramic film on a substrate by mixing a fine particle of a raw material species which becomes at least part of raw materials for ceramics with an active species, and feeding the mixed fine particle and active species to the substrate. A manufacture device includes a disposing section which also serves as a heating section for a substrate, a raw material species feeding section for feeding a fine particle of a raw material species, an active species feeding section for feeding an active species, and a mixing section for mixing the raw material species and the active species.

Abstract: A method of manufacturing a ceramic film includes a step of forming a ceramic film 30 by crystallizing a raw material body 20. The raw material body 20 contains different types of raw materials in a mixed state. The different types of raw materials differ from one another in at least one of a crystal growth condition and a crystal growth mechanism in the crystallization of the raw materials. According to this manufacturing method, a surface morphology of the ceramic film can be improved.

Abstract: A ferroelectric memory device of the present invention includes a memory cell array in which memory cells are arranged in a matrix having first signal electrodes, second signal electrodes arranged in a direction intersecting the first signal electrodes, and a ferroelectric layer disposed at least in intersection regions between the first signal electrodes and the second signal electrodes, and a peripheral circuit section for selectively writing information into or reading information from the memory cell. The memory cell array and the peripheral circuit section are formed in different layers. The peripheral circuit section is formed in a region outside the memory cell array.

Abstract: The present invention relates to: a memory cell array which is capable of decreasing the parasitic capacitance of signal electrodes and has ferroelectric layers making up ferroelectric capacitors and having a predetermined pattern; a method of fabricating the memory cell array, and a ferroelectric memory device. In the memory cell array, memory cells formed of ferroelectric capacitors are arranged in a matrix. The ferroelectric capacitors include first signal electrodes, second signal electrodes arranged in a direction intersecting the first signal electrodes, and ferroelectric layers disposed linearly along either the first signal electrodes or the second signal electrodes. Alternatively, the ferroelectric layers may be disposed only in intersection areas of the first and second signal electrodes.

Abstract: A ceramics fabricating method which includes a step of forming a ceramic film by feeding an electromagnetic wave and an active species of a substance which is at least part of raw materials for the ceramics to a predetermined region. A film including a substance which is part of the raw materials for the ceramics may be formed in the predetermined region. The fabrication method further includes a step of feeding the active species and the electromagnetic wave to a first ceramic film to form a second ceramic film which has a crystal structure differing from that of the first ceramic film.

Abstract: A ferroelectric memory according to the present invention includes a passive matrix array in which memory cells formed of ferroelectric capacitors are arranged, and a peripheral circuit for the passive matrix array. The passive matrix array is formed of a passive matrix array microchip, and the peripheral circuit such as a word line driver circuit or a bit line driver circuit is formed on a peripheral circuit substrate, thereby integrating the passive matrix array microchip on the peripheral circuit substrate. Since this allows the passive matrix array and the peripheral circuit therefor to be separately fabricated, the peripheral circuit is not adversely affected when fabricating the passive matrix array, thereby decreasing the degree of limitation in the fabrication process.

Abstract: A ferroelectric memory device includes a memory cell array and a peripheral circuit section. The memory cell array, in which memory cells are arranged in a matrix, includes first signal electrodes, second signal electrodes which are arranged in a direction so as to intersect the first signal electrodes, and a ferroelectric layer disposed at least at intersection regions between the first signal electrodes and the second signal electrodes. The peripheral circuit section includes circuits for selectively allowing information to be written into or read from the memory cells, such as a first driver circuit, a second driver circuit, and a signal detection circuit. The memory cell array and the peripheral circuit section are disposed in different layers so as to be layered. This ferroelectric memory device can significantly increase the degree of integration of the memory cells and decrease the chip area.

Abstract: The present invention is equipped with a ferroelectric film (13) having concave and convex patterns formed on both sides thereof corresponding to respective electrodes of a plurality of capacitors, a first substrate (14) having one electrodes of the plurality of capacitors formed on one surface thereof, a second substrate (18) having the other electrodes of the plurality of capacitors formed on the other surface thereof, and first and second anisotropic conduction films (16,17) that are provided between one surface of the ferroelectric film and the first substrate and between the other surface of the ferroelectric film and the second electrode film, respectively, to thereby establish conduction between the convex sections of the ferroelectric film of the capacitors and the electrodes of the capacitors.

Abstract: This is an invention of a superconductive device that is equipped with a first superconductive electrode, a second superconductive electrode and a junction that is made of a superconductive material that connects these superconductive electrodes, wherein there are 2-terminal or 3-terminal superconductive devices that use a junction that is in a superconductive state that is weaker than the first and the second superconductive electrodes or in a normal conductive state that is near the superconductive state. The differences between the critical current, the critical temperature, the pair potential and the carrier densities of the first and the second superconductive electrodes and the junction are used as a means of putting the junction in the states mentioned above. Based on the methods mentioned above, a superconductive device which has few pattern rule restrictions and which is easy to fabricate can be offered.