Patents by Inventor Eiji Watanabe

Eiji Watanabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7042741
    Abstract: It is an object of the invention to provide a PWM inverter control method capable of causing a reduction in a noise and energy saving to be consistent with each other by the reduction in a noise and the limit of the number of switching operations.
    Type: Grant
    Filed: May 26, 2003
    Date of Patent: May 9, 2006
    Assignee: Kabushiki Kaisha Yaskawa Denki
    Inventors: Yoshiyuki Tanaka, Katsutoshi Yamanaka, Eiji Watanabe
  • Patent number: 7031172
    Abstract: It is an object of the invention to provide a multilevel PWM inverter control apparatus capable of safely carrying out switching from a normal operation to a protecting operation and performing a reset from the protecting operation to the normal run safely and smoothly without requiring a complicated control algorithm. In the invention, if a current value I which is measured is set to have a level which is equal to or higher than the level of a first reference value I1 and is lower than the level of a second reference value I2, a zero vector to be started from an OOO state in which an intermediate potential is output for all of phases is output (Step 22). If the current value I is set to have a level which is equal to or higher than the level of the second reference value I2 and is lower than the level of a third reference value I3, a base block operation for bringing all of switching units into an OFF state is carried out after outputting the zero vector (Step 28).
    Type: Grant
    Filed: June 4, 2003
    Date of Patent: April 18, 2006
    Assignee: Kabushiki Kaisha Yaskawa Denki
    Inventors: Yoshiyuki Tanaka, Katsutoshi Yamanaka, Eiji Watanabe
  • Publication number: 20060067093
    Abstract: It is an object of the invention to provide a PWM inverter control method capable of causing a reduction in a noise and energy saving to be consistent with each other by the reduction in a noise and the limit of the number of switching operations.
    Type: Application
    Filed: May 26, 2003
    Publication date: March 30, 2006
    Inventors: Yoshiyuki Tanaka, Katsutoshi Yamanaka, Eiji Watanabe
  • Publication number: 20060067345
    Abstract: There is provided a packet processing device for, when decoding variable length data that is split into packets, realizing a reduction in processing load at a decoder, by providing information for identifying a start position of the data. A header analyzing section (11) determines whether data stored in a packet is start data containing start information or other data. A data extracting section (12) extracts data from a packet and stores the data in a buffer (13). A buffer controlling section (14) causes a start position memory (15) and a number-of-starts counter (16) to retain an address position and the number of start data stored in the buffer (13). A decode section (20) refers to the start position memory (15) and the number-of-starts counter (16) and executes a decode process for the data stored in the buffer (13).
    Type: Application
    Filed: June 7, 2004
    Publication date: March 30, 2006
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shigeo Hayashi, Eiji Watanabe, Hidekatsu Ozeki
  • Publication number: 20060056211
    Abstract: It is an object of the invention to provide a multilevel PWM inverter control apparatus capable of safely carrying out switching from a normal operation to a protecting operation and performing a reset from the protecting operation to the normal run safely and smoothly without requiring a complicated control algorithm. In the invention, if a current value I which is measured is set to have a level which is equal to or higher than the level of a first reference value I1 and is lower than the level of a second reference value I2, a zero vector to be started from an OOO state in which an intermediate potential is output for all of phases is output (Step 22). If the current value I is set to have a level which is equal to or higher than the level of the second reference value I2 and is lower than the level of a third reference value I3, a base block operation for bringing all of switching units into an OFF state is carried out after outputting the zero vector (Step 28).
    Type: Application
    Filed: June 4, 2003
    Publication date: March 16, 2006
    Inventors: Yoshiyuki Tanaka, Katsutoshi Yamanaka, Eiji Watanabe
  • Publication number: 20060027214
    Abstract: An inlet port 16 communicating with the interior of a fuel delivery pipe body 10 to introduce fuel is made open in a center of a tubular joint 11 having a smaller diameter than an inside diameter of a holder portion 15 of an injector 32 connected to a respective pipe end portion 25, and a length from a center of this inlet port 16 to the pipe end portion 25 is set to 30 to 1000 mm, to thereby form the tubular joint 11. The tubular joint 11 and the fuel delivery pipe body 10 are fixed such that the inlet port 16 of this tubular joint 11 is communicatable with the interior of the fuel delivery pipe body 10.
    Type: Application
    Filed: August 2, 2005
    Publication date: February 9, 2006
    Inventors: Eiji Watanabe, Koichi Hayashi, Shoichiro Usui
  • Publication number: 20050257774
    Abstract: A fuel delivery pipe capable of reducing a pressure pulsation at the time of a fuel injection due to injection nozzles, preventing vibrations and noises at an underfloor pipe arrangement, and turning down a radiate sound from the fuel delivery pipe, wherein a flexible absorbing wall surface 10 formed on a wall surface of a fuel delivery body 1 is loosened due to internal pressure changes to render internal volume of the fuel delivery body 1 increasable, ?L/{square root}{square root over ( )}V determined by sonic speed ?L of fuel flowing through the fuel delivery body 1 and the internal volume V of the fuel delivery body 1 is set as 20×103(m?0.5·sec?1)??L/{square root}{square root over ( )}V?85×103(m?0.5·sec?1) while a ratio ?L/?H of equivalent sonic speed ?H in a high frequency area to the sonic speed ?L of the fuel is set as ?L/?H?0.
    Type: Application
    Filed: October 8, 2003
    Publication date: November 24, 2005
    Inventors: Masayoshi Usui, Eiji Watanabe, Hikari Tsuchiya, Yoshiyuki Serizawa, Kazuteru Mizuno, Koichi Hayashi, Tetsuo Ogata
  • Patent number: 6933422
    Abstract: An object of the present invention is to provide a null mutant non-human animal showing salt intake behavior similar to that of wild-type animals under water-sufficient conditions and showing much more intakes of hypertonic saline compared with wild-type animals under water- and salt-depleted conditions, for example, an Nav2 gene-deficient non-human animal, which is useful as a model animal of excessive salt intake experiments. The object will be attained by following process: mouse genomic libraries are screened with rat NaG cDNA as a probe, then Nav2 gene of genomic DNA is isolated, and a targeting vector is constructed by inserting marker gene such as neo gene into the exon of Nav2. After thus constructed targeting vector is induced to ES cells, homologously recombined ES cells are selected, then germ line chimeric mice are constructed with this ES cells strain, and they are hybridized with the wild-type mice and heterozygous mutant mice are obtained.
    Type: Grant
    Filed: August 3, 2001
    Date of Patent: August 23, 2005
    Assignee: Japan as represented by Director of General of Okazaki National Research Institute
    Inventors: Masaharu Noda, Eiji Watanabe
  • Publication number: 20050151250
    Abstract: A semiconductor device includes a substrate, a pad electrode formed on the substrate and a bump electrode formed on the pad electrode, wherein the pad electrode has an irregular flaw, and there is provided a pattern covering the irregular flaw between the pad electrode an the bump electrode.
    Type: Application
    Filed: November 29, 2004
    Publication date: July 14, 2005
    Inventors: Shuichi Chiba, Masahiko Ishiguri, Koichi Murata, Eiji Watanabe, Michiaki Tamagawa, Akira Satoh, Yasushi Toida, Kazuhiro Misawa
  • Patent number: 6917685
    Abstract: A key generator (51, 61) generates, from an IP-key (11) for entering a closed IP network (1), a set (52, 62) of session keys (53, 63) indexed for identification, an index pointer (71, 72) points an index (i, j) to identify a session key (53, 63), the set (52, 62) of session keys has a divergence barrier incorporated therein for barring a computational approach to any session key (53, 63), and an unbar data set (i, j, 62) unbars the divergence barrier.
    Type: Grant
    Filed: February 4, 1999
    Date of Patent: July 12, 2005
    Assignee: Meteora System Co., Ltd.
    Inventors: Eiji Watanabe, Hiroshi Take, Yoshihiro Sekiguchi, Tomo Yamada, Yasuo Tojima
  • Patent number: 6905951
    Abstract: A semiconductor device substrate has fine terminals with a small pitch and is able to be easily produced at a low cost without using a special process. A mounting terminal has a pyramidal shape and extending between a front surface and a back surface of a silicon substrate. An end of the mounting terminal protrudes from the back surface of the silicon substrate. A wiring layer is formed on the front surface of the silicon substrate. The wiring layer includes a conductive layer that is electrically connected to the mounting terminal.
    Type: Grant
    Filed: June 8, 2004
    Date of Patent: June 14, 2005
    Assignee: Fujitsu Limited
    Inventors: Yoshiyuki Yoneda, Masaharu Minamizawa, Eiji Watanabe, Mitsutaka Sato
  • Publication number: 20050062871
    Abstract: A solid-state imaging device, comprises: a semiconductor substrate having a first surface; a solid-state imaging element in the first surface of the semiconductor substrate, the solid-state imaging element comprising a light-receiving region; a light-transmission member having a second surface and a third surface, the second surface being opposite to the third surface, wherein the light-transmission member and the first surface of the semiconductor substrate define a gap between the second surface of the light-transmission member and an outer surface of the light-receiving region; and an external connection terminal connected to the solid-state imaging element, wherein a distance between the outer surface of the light-receiving region and the third surface of the light-transmission member is 0.5 mm or more.
    Type: Application
    Filed: August 2, 2004
    Publication date: March 24, 2005
    Inventors: Kazuhiro Nishida, Hiroshi Maeda, Yoshihisa Negishi, Shunichi Hosaka, Masatoshi Yasumatsu, Eiji Watanabe
  • Publication number: 20050024519
    Abstract: A solid-state imaging device, comprises: a semiconductor substrate having a first surface; a solid-state imaging element in the first surface of semiconductor substrate, the solid-state imaging element comprising a light-receiving region; a light-transmission member having a second surface and a third surface, the second surface being opposite to the third surface, wherein the light-transmission member and the first surface of the semiconductor substrate define a gap between the second surface of the light-transmission member and an outer surface of the light-receiving region; and an external connection terminal connected to the solid-state imaging element, wherein the light-transmission member comprises low ?-ray glass.
    Type: Application
    Filed: July 22, 2004
    Publication date: February 3, 2005
    Inventors: Kazuhiro Nishida, Hiroshi Maeda, Yoshihisa Negishi, Shunichi Hosaka, Eiji Watanabe, Masatoshi Yasumatsu
  • Publication number: 20050006792
    Abstract: A method of manufacturing a semiconductor device includes the steps of forming barrier metals on first electrodes provided on a chip of the semiconductor device, implementing a predetermined test on the semiconductor device by applying a signal to the semiconductor device via at least one of the barrier metals, and forming second protruded electrodes on the barrier metals. The predetermined tests are implemented before forming second protruded electrodes on the barrier metals.
    Type: Application
    Filed: August 10, 2004
    Publication date: January 13, 2005
    Applicant: FUJITSU LIMITED
    Inventors: Katsumi Miyata, Eiji Watanabe, Hiroyuki Yoda
  • Publication number: 20040232549
    Abstract: A method of manufacturing a semiconductor device using a wiring substrate is provided which can facilitate the handling of the wiring substrate. The method includes the steps of forming a peelable resin layer on a silicon substrate, forming the wiring substrate on the peelable resin layer, mounting semiconductor chips on the wiring substrate, forming semiconductor devices by sealing the plurality of semiconductor chips by a sealing resin, individualizing the semiconductor devices by dicing the semiconductor devices from the sealing resin side but leaving the silicon substrate, peeling each of the individualized semiconductor devices from the silicon substrate between the silicon substrate and the peelable resin layer, and exposing terminals on the wiring substrate by forming openings through the peelable resin layer or by removing the peelable resin layer.
    Type: Application
    Filed: June 29, 2004
    Publication date: November 25, 2004
    Applicant: FUJITSU LIMITED
    Inventors: Nobukatsu Saito, Masaharu Minamizawa, Yoshiyuki Yoneda, Nobutaka Shimizu, Kazuyuki Imamura, Atsushi Kikuchi, Tadahiro Okamoto, Eiji Watanabe
  • Publication number: 20040224499
    Abstract: A semiconductor device substrate has fine terminals with a small pitch and is able to be easily produced at a low cost without using a special process. A mounting terminal has a pyramidal shape and extending between a front surface and a back surface of a silicon substrate. An end of the mounting terminal protrudes from the back surface of the silicon substrate. A wiring layer is formed on the front surface of the silicon substrate. The wiring layer includes a conductive layer that is electrically connected to the mounting terminal.
    Type: Application
    Filed: June 8, 2004
    Publication date: November 11, 2004
    Applicant: FUJITSU LIMITED
    Inventors: Yoshiyuki Yoneda, Masaharu Minamizawa, Eiji Watanabe, Mitsutaka Sato
  • Patent number: 6795323
    Abstract: On the basis of: a first calculated value ic which is a product of a calculated value of a time of three-phase output voltages in a state where a positive bus, a negative bus, and a neutral line are connected respectively to three-phase phase output terminals, and a predicted neutral current value in the state; and second and third calculated values icx and icy which are products of a calculated value of a time of the three-phase output voltages that can take state 1 where two of the three-phase phase output terminals are connected to the positive bus or the neutral line, and a remaining one terminal is connected to the neutral line or the negative bus, and state 2 opposite to the state, and predicted neutral current values in states 1 and 2, a time ratio of state 1 and 2 during a PWM period is determined so as to make a current flowing through the neutral line close to zero, or a potential of the neutral line of the three-phase output voltages close to a voltage which is exactly the middle between voltages o
    Type: Grant
    Filed: June 6, 2003
    Date of Patent: September 21, 2004
    Assignee: Kabushiki Kaisha Yaskawa Denki
    Inventors: Yoshiyuki Tanaka, Katsutoshi Yamanaka, Eiji Watanabe
  • Patent number: 6794273
    Abstract: A method of manufacturing a semiconductor device using a wiring substrate is provided which can facilitate the handling of the wiring substrate. The method includes the steps of forming a peelable resin layer on a silicon substrate, forming the wiring substrate on the peelable resin layer, mounting semiconductor chips on the wiring substrate, forming semiconductor devices by sealing the plurality of semiconductor chips by a sealing resin, individualizing the semiconductor devices by dicing the semiconductor devices from the sealing resin side but leaving the silicon substrate, peeling each of the individualized semiconductor devices from the silicon substrate between the silicon substrate and the peelable resin layer, and exposing terminals on the wiring substrate by forming openings through the peelable resin layer or by removing the peelable resin layer.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: September 21, 2004
    Assignee: Fujitsu Limited
    Inventors: Nobukatsu Saito, Masaharu Minamizawa, Yoshiyuki Yoneda, Nobutaka Shimizu, Kazuyuki Imamura, Atsushi Kikuchi, Tadahiro Okamoto, Eiji Watanabe
  • Patent number: 6781224
    Abstract: A semiconductor device substrate has fine terminals with a small pitch and is able to be easily produced at a low cost without using a special process. A mounting terminal has a pyramidal shape and extending between a front surface and a back surface of a silicon substrate. An end of the mounting terminal protrudes from the back surface of the silicon substrate. A wiring layer is formed on the front surface of the silicon substrate. The wiring layer includes a conductive layer that is electrically connected to the mounting terminal.
    Type: Grant
    Filed: October 2, 2002
    Date of Patent: August 24, 2004
    Assignee: Fujitsu Limited
    Inventors: Yoshiyuki Yoneda, Masaharu Minamizawa, Eiji Watanabe, Mitsutaka Sato
  • Patent number: 6751105
    Abstract: For an interval in which an Op-vector and a b-vector are successively output among intervals of output voltage vectors of each phase within a PWM cycle, the output times of each vector are divided by a positive integer m to find divided times of each vector, and the Op-vector and the b-vector are each alternately output for the divided time, each vector being output m times. For an interval in which an On-vector and an a-vector are successively output, the output times of each vector are divided by a positive integer n to find divided times of each vector, and the On-vector and a-vector are each alternately output for the divided time, each vector being output n times. The adoption of this method enables dispersion of the frequency component of current ripple that arises from PWM pulses (1)-(3).
    Type: Grant
    Filed: November 18, 2002
    Date of Patent: June 15, 2004
    Assignee: Kabushiki Kaisha Yasakawa Denki
    Inventors: Katsutoshi Yamanaka, Eiji Watanabe, Takaaki Terada, Yoshiyuki Tanaka, Yuuichi Terazono