Patents by Inventor Eisuke Nishitani
Eisuke Nishitani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20090130860Abstract: To remove the deposit including a high dielectric constant film deposited on an inside of a processing chamber, by using a cleaning gas activated only by heat. The method includes the steps of: loading a substrate or a plurality of substrates into the processing chamber; performing processing to deposit the high dielectric constant film on the substrate by supplying processing gas into the processing chamber; unloading the processed substrate from the inside of the processing chamber; and cleaning the inside of the processing chamber by supplying a halide gas and an oxygen based gas into the processing chamber, and removing the deposit including the high dielectric constant film deposited on the inside of the processing chamber, and in the step of cleaning the inside of the processing chamber, the concentration of the oxygen based gas in the halide gas and the oxygen based gas is set to be less than 7%.Type: ApplicationFiled: July 8, 2008Publication date: May 21, 2009Applicants: HITACHI KOKUSAI ELECTRIC INC., TAIYO NIPPON SANSO CORPORATIONInventors: Hironobu Miya, Eisuke Nishitani, Yuji Takebayashi, Masanori Sakai, Hirohisa Yamazaki, Toshinori Shibata, Minoru Inoue
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Patent number: 7300833Abstract: When an oxidation treatment for regenerating a gate insulating film 6 is performed after forming gate electrodes 7A of a polymetal structure in which a WNx film and a W film are stacked on a polysilicon film, a wafer 1 is heated and cooled under conditions for reducing a W oxide 27 on the sidewall of each gate electrode 7A. As a result, the amount of the W oxide 27 to be deposited on the surface of the wafer 1 is reduced.Type: GrantFiled: October 27, 2006Date of Patent: November 27, 2007Assignee: Renesas Technology Corp.Inventors: Naoki Yamamoto, Hiroyuki Uchiyama, Norio Suzuki, Eisuke Nishitani, Shin'ichiro Kimura, Kazuyuki Hozawa
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Publication number: 20070048917Abstract: When an oxidation treatment for regenerating a gate insulating film 6 is performed after forming gate electrodes 7A of a polymetal structure in which a WNx film and a W film are stacked on a polysilicon film, a wafer 1 is heated and cooled under conditions for reducing a W oxide 27 on the sidewall of each gate electrode 7A. As a result, the amount of the W oxide 27 to be deposited on the surface of the wafer 1 is reduced.Type: ApplicationFiled: October 27, 2006Publication date: March 1, 2007Inventors: Naoki Yamamoto, Hiroyuki Uchiyama, Norio Suzuki, Eisuke Nishitani, Shin'ichiro Kimura, Kazuyuki Hozawa
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Patent number: 7144766Abstract: When an oxidation treatment for regenerating a gate insulating film 6 is performed after forming gate electrodes 7A of a polymetal structure in which a WNx film and a W film are stacked on a polysilicon film, a wafer 1 is heated and cooled under conditions for reducing a W oxide 27 on the sidewall of each gate electrode 7A. As a result, the amount of the W oxide 27 to be deposited on the surface of the wafer 1 is reduced.Type: GrantFiled: August 8, 2005Date of Patent: December 5, 2006Assignee: Renesas Technology Corp.Inventors: Naoki Yamamoto, Hiroyuki Uchiyama, Norio Suzuki, Eisuke Nishitani, Shin'ichiro Kimura, Kazuyuki Hozawa
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Patent number: 7049187Abstract: When an oxidation treatment for regenerating a gate insulating film 6 is performed after forming gate electrodes 7A of a polymetal structure in which a WNx film and a W film are stacked on a polysilicon film, a wafer 1 is heated and cooled under conditions for reducing a W oxide 27 on the sidewall of each gate electrode 7A. As a result, the amount of the W oxide 27 to be deposited on the surface of the wafer 1 is reduced.Type: GrantFiled: October 31, 2001Date of Patent: May 23, 2006Assignee: Renesas Technology Corp.Inventors: Naoki Yamamoto, Hiroyuki Uchiyama, Norio Suzuki, Eisuke Nishitani, Shin'ichiro Kimura, Kazuyuki Hozawa
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Publication number: 20060075972Abstract: A substrate processing apparatus comprises a processing chamber; a susceptor on which a substrate to be processed is to be placed; and a heating unit disposed below the susceptor for heating the substrate to be processed placed on the susceptor. The susceptor and the heating unit are accommodated in the processing chamber, and in a state in which the susceptor and the heating unit are relatively rotated, the substrate to be processed is processed. At least the susceptor is lifted and lowered in the processing chamber, and a substrate to be processed lifting and lowering apparatus for lifting and lowering the substrate to be processed with respect to at least a portion of the susceptor is disposed in the processing chamber.Type: ApplicationFiled: October 25, 2005Publication date: April 13, 2006Inventors: Seiyo Nakashima, Michiko Nishiwaki, Yukinori Aburatani, Satoshi Okada, Eisuke Nishitani, Kazuhiro Nakagomi, Kazuhito Ikeda, Kazuhiro Shimeno, Gakuji Ohta, Katsuhisa Kasanami
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Publication number: 20060009046Abstract: When an oxidation treatment for regenerating a gate insulating film 6 is performed after forming gate electrodes 7A of a polymetal structure in which a WNx film and a W film are stacked on a polysilicon film, a wafer 1 is heated and cooled under conditions for reducing a W oxide 27 on the sidewall of each gate electrode 7A. As a result, the amount of the W oxide 27 to be deposited on the surface of the wafer 1 is reduced.Type: ApplicationFiled: August 8, 2005Publication date: January 12, 2006Inventors: Naoki Yamamoto, Hiroyuki Uchiyama, Norio Suzuki, Eisuke Nishitani, Shin'ichiro Kimura, Kazuyuki Hozawa
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Patent number: 6905928Abstract: When polycrystalline silicon germanium film is used for gate electrodes in a MOS transistor apparatus, there have been problems of reduced reliability in the gate insulating film, due to stress in the silicon germanium grains. Therefore, a polysilicon germanium film is formed, after forming silicon fine particles of particle size 10 nm or less on an oxide film. As a result, it is possible to achieve a high-speed MOS transistor apparatus using an ultra-thin oxide film having a film thickness of 1.5 nm or less, wherein the Ge concentration of the polycrystalline silicon germanium at its interface with the oxide film is uniform, thereby reducing the stress in the film, and improving the reliability of the gate electrode.Type: GrantFiled: May 9, 2002Date of Patent: June 14, 2005Assignee: Hitachi, Ltd.Inventors: Naoki Kanda, Arito Ogawa, Eisuke Nishitani, Miwako Nakahara, Tadanori Yoshida, Kiyoshi Ogata
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Patent number: 6875280Abstract: A substrate processing apparatus includes a chamber, a gas introducing portion, a gas discharge port, a substrate transfer gate, and a substrate moving member which moves the substrate between a substrate processing position where the substrate is processed in the chamber and a substrate transferring in-out position in the chamber where the substrate transferred into the chamber from the substrate transfer gate is located and where the substrate is located when the substrate is transferred out from the chamber through the substrate transfer gate. The gas introducing portion, the substrate processing position, the gas discharge port and the substrate transfer gate are disposed in this order. A gas restraining member which restrains processing gas for processing the substrate from flowing toward the substrate transfer gate is provided between the gas discharge port and the substrate transfer gate.Type: GrantFiled: February 9, 2001Date of Patent: April 5, 2005Assignee: Hitachi Kokusai Electric IncInventors: Kazuhito Ikeda, Eisuke Nishitani, Harunobu Sakuma, Kazuhiro Nakagomi
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Patent number: 6870224Abstract: When polycrystalline silicon germanium film is used for gate electrodes in a MOS transistor apparatus, there have been problems of reduced reliability in the gate insulating film, due to stress in the silicon germanium grains. Therefore, a polysilicon germanium film is formed, after forming silicon fine particles of particle size 10 nm or less on an oxide film. As a result, it is possible to achieve a high-speed MOS transistor apparatus using an ultra-thin oxide film having a film thickness of 1.5 nm or less, wherein the Ge concentration of the polycrystalline silicon germanium at its interface with the oxide film is uniform, thereby reducing the stress in the film, and improving the reliability of the gate electrode.Type: GrantFiled: August 15, 2003Date of Patent: March 22, 2005Assignee: Hitachi, Ltd.Inventors: Naoki Kanda, Arito Ogawa, Eisuke Nishitani, Miwako Nakahara, Tadanori Yoshida, Kiyoshi Ogata
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Publication number: 20040145001Abstract: When polycrystalline silicon germanium film is used for gate electrodes in a MOS transistor apparatus, there have been problems of reduced reliability in the gate insulating film, due to stress in the silicon germanium grains. Therefore, a polysilicon germanium film is formed, after forming silicon fine particles of particle size 10 nm or less on an oxide film. As a result, it is possible to achieve a high-speed MOS transistor apparatus using an ultra-thin oxide film having a film thickness of 1.5 nm or less, wherein the Ge concentration of the polycrystalline silicon germanium at its interface with the oxide film is uniform, thereby reducing the stress in the film, and improving the reliability of the gate electrode.Type: ApplicationFiled: August 15, 2003Publication date: July 29, 2004Applicant: Hitachi, Ltd., IncorporationInventors: Naoki Kanda, Arito Ogawa, Eisuke Nishitani, Miwako Nakahara, Tadanori Yoshida, Kiyoshi Ogata
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Publication number: 20040063276Abstract: When an oxidation treatment for regenerating a gate insulating film 6 is performed after forming gate electrodes 7A of a polymetal structure in which a WNx film and a W film are stacked on a polysilicon film, a wafer 1 is heated and cooled under conditions for reducing a W oxide 27 on the sidewall of each gate electrode 7A. As a result, the amount of the W oxide 27 to be deposited on the surface of the wafer 1 is reduced.Type: ApplicationFiled: August 20, 2003Publication date: April 1, 2004Inventors: Naoki Yamamoto, Hiroyuki Uchiyama, Norio Suzuki, Eisuke Nishitani, Shin?apos;ichiro Kimura, Kazuyuki Hozawa
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Publication number: 20040051139Abstract: When polycrystalline silicon germanium film is used for gate electrodes in a MOS transistor apparatus, there have been problems of reduced reliability in the gate insulating film, due to stress in the silicon germanium grains. Therefore, a polysilicon germanium film is formed, after forming silicon fine particles of particle size 10 nm or less on an oxide film. As a result, it is possible to achieve a high-speed MOS transistor apparatus using an ultra-thin oxide film having a film thickness of 1.5 nm or less, wherein the Ge concentration of the polycrystalline silicon germanium at its interface with the oxide film is uniform, thereby reducing the stress in the film, and improving the reliability of the gate electrode.Type: ApplicationFiled: August 15, 2003Publication date: March 18, 2004Applicant: Hitachi, LtdInventors: Naoki Kanda, Arito Ogawa, Eisuke Nishitani, Miwako Nakahara, Tadanori Yoshida, Kiyoshi Ogata
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Publication number: 20030183901Abstract: When polycrystalline silicon germanium film is used for gate electrodes in a MOS transistor apparatus, there have been problems of reduced reliability in the gate insulating film, due to stress in the silicon germanium grains. Therefore, a polysilicon germanium film is formed, after forming silicon fine particles of particle size 10 nm or less on an oxide film. As a result, it is possible to achieve a high-speed MOS transistor apparatus using an ultra-thin oxide film having a film thickness of 1.5 nm or less, wherein the Ge concentration of the polycrystalline silicon germanium at its interface with the oxide film is uniform, thereby reducing the stress in the film, and improving the reliability of the gate electrode.Type: ApplicationFiled: May 9, 2002Publication date: October 2, 2003Applicant: Hitachi, Ltd.Inventors: Naoki Kanda, Arito Ogawa, Eisuke Nishitani, Miwako Nakahara, Tadanori Yoshida, Kiyoshi Ogata
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Patent number: 6541344Abstract: A substrate processing apparatus includes a heater which heats a substrate through a susceptor on which the substrate is placed. The heater is divided into a plurality of zone heaters, and a reflecting member is interposed between at least two of the plurality of zone heaters.Type: GrantFiled: October 16, 2001Date of Patent: April 1, 2003Assignee: Hitachi Kokusai Electric Inc.Inventors: Katsuhisa Kasanami, Eisuke Nishitani, Michiko Nishiwaki, Satoshi Okada
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Patent number: 6514869Abstract: In a semiconductor device manufacturing method for processing a plurality of substrates by alternately repeating a pretreatment stage and a continuous substrate processing stage, the continuous substrate processing stage comprises the steps of: loading a substrate on a heater unit located at a substrate loading/unloading position, the heater unit supporting and heating the substrate; processing the loaded substrate after transferring the heater unit having thereon the loaded substrate to a substrate processing position; unloading the processed substrate; and repeating the loading step, the processing step and the unloading step until a set of substrates are processed, and wherein the pretreatment stage is carried out by maintaining the heater unit between the substrate loading/unloading position and the substrate processing position.Type: GrantFiled: August 9, 2001Date of Patent: February 4, 2003Assignee: Hitachi Kokusai Electric Inc.Inventors: Tetsuya Wada, Toshimitsu Miyata, Eisuke Nishitani
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Patent number: 6483989Abstract: A substrate processing apparatus is disclosed for heating a substrate by a heater through a susceptor in a state in which the substrate is placed on the susceptor, to process the substrate. The heater is divided into a plurality of respectively controlled zone heaters to form gaps therebetween, a center position of a gap of the gaps which is positioned closer to an end of the substrate than any other gap is located in a range from an inner side 10 mm to an outer side 6 mm in a radial direction of the substrate with respect to the end of the substrate.Type: GrantFiled: November 8, 2001Date of Patent: November 19, 2002Assignee: Hitachi Kokusai Electric Inc.Inventors: Satoshi Okada, Michiko Nishiwaki, Katsuhisa Kasanami, Eisuke Nishitani
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Publication number: 20020160560Abstract: A substrate processing apparatus is disclosed for heating a substrate by a heater through a susceptor in a state in which the substrate is placed on the susceptor, to process the substrate. The heater is divided into a plurality of respectively controlled zone heaters to form gaps therebetween, a center position of a gap of the gaps which is positioned closer to an end of the substrate than any other gap is located in a range from an inner side 10 mm to an outer side 6 mm in a radial direction of the substrate with respect to the end of the substrate.Type: ApplicationFiled: November 8, 2001Publication date: October 31, 2002Inventors: Satoshi Okada, Michiko Nishiwaki, Katsuhisa Kasanami, Eisuke Nishitani
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Patent number: 6472639Abstract: Uniformity of temperature is established within a wafer, and a higher throughput is achieved while the wafer heating time is dramatically reduced by combining lamp heating with hot-wall heating. Lamps 10 are provided outside the furnace body 3 of a hot-wall CVD apparatus. The hot-wall reactor furnace body 3 is preheated to a prescribed temperature. Wafers W are loaded into the furnace body 3, and these wafers W are rapidly heated mediately thereafter to the desired temperature by light emitted by the lamps 10. The lamps 10 are switched off following heating, and the wafer temperature is allowed to reach a uniform state as a result of heat diffusion in the wafers in the hot-wall reactor furnace body 3. It is also possible to adopt an arrangement in which preheating commensurate with the cooling occurring during the transport period is performed before the wafers W are loaded into the furnace body 3. the wafers W are then loaded into the reactor furnace body 3.Type: GrantFiled: March 29, 2002Date of Patent: October 29, 2002Assignee: Kokusai Electric Co., Ltd.Inventors: Eisuke Nishitani, Katsuhisa Kasanami, Naoko Matsuyama, Shinya Sasaki
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Publication number: 20020096507Abstract: Uniformity of temperature is established within a wafer, and a higher throughput is achieved while the wafer heating time is dramatically reduced by combining lamp heating with hot-wall heating. Lamps 10 are provided outside the furnace body 3 of a hot-wall CVD apparatus. The hot-wall reactor furnace body 3 is preheated to a prescribed temperature. Wafers W are loaded into the furnace body 3, and these wafers W are rapidly heated immediately thereafter to the desired temperature by light emitted by the lamps 10. The lamps 10 are switched off following heating, and the wafer temperature is allowed to reach a uniform state as a result of heat diffusion in the wafers in the hot-wall reactor furnace body 3. It is also possible to adopt an arrangement in which preheating commensurate with the cooling occurring during the transport period is performed before the wafers W are loaded into the furnace body 3, the wafers W are then loaded Into the reactor furnace body 3.Type: ApplicationFiled: March 29, 2002Publication date: July 25, 2002Applicant: Kokusai Electric Co., Ltd.Inventors: Eisuke Nishitani, Katsuhisa Kasanami, Naoko Matsuyama, Shinya Sasaki