Patents by Inventor Eisuke Nishitani

Eisuke Nishitani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6414280
    Abstract: Uniformity of temperature is established within a wafer, and a higher throughput is achieved while the wafer heating time is dramatically reduced by combining lamp heating with hot-wall heating. Lamps 10 are provided outside the furnace body 3 of a hot-wall CVD apparatus. The hot-wall reactor furnace body 3 is preheated to a prescribed temperature. Wafers W are loaded into the furnace body 3, and these wafers W are rapidly heated immediately thereafter to the desired temperature by light emitted by the lamps 10. The lamps 10 are switched off following heating, and the wafer temperature is allowed to reach a uniform state as a result of heat diffusion in the wafers in the hot-wall reactor furnace body 3.
    Type: Grant
    Filed: March 30, 2000
    Date of Patent: July 2, 2002
    Assignee: Kokusai Electric Co., Ltd.
    Inventors: Eisuke Nishitani, Katsuhisa Kasanami, Naoko Matsuyama, Shinya Sasaki
  • Publication number: 20020072165
    Abstract: In a substrate processing apparatus for heating a substrate by a heater through a susceptor in a state in which the substrate is placed on the susceptor, to process the substrate, the heater is divided into a plurality of zone heaters, and a reflecting member is interposed between at least two of the plurality of zone heaters. Preferably, space exists between the susceptor and the heater. Preferably, the heater is divided into an outer peripheral zone heater and at least one inner zone heater inside the outer peripheral zone heater, the reflecting member has a recessed cross section, and the reflecting member surrounds the inner zone heater except the outer peripheral zone heater.
    Type: Application
    Filed: October 16, 2001
    Publication date: June 13, 2002
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Katsuhisa Kasanami, Eisuke Nishitani, Michiko Nishiwaki, Satoshi Okada
  • Publication number: 20020034862
    Abstract: In a semiconductor device manufacturing method for processing a plurality of substrates by alternately repeating a pretreatment stage and a continuous substrate processing stage, the continuous substrate processing stage comprises the steps of: loading a substrate on a heater unit located at a substrate loading/unloading position, the heater unit supporting and heating the substrate; processing the loaded substrate after transferring the heater unit having thereon the loaded substrate to a substrate processing position; unloading the processed substrate; and repeating the loading step, the processing step and the unloading step until a set of substrates are processed, and wherein the pretreatment stage is carried out by maintaining the heater unit between the substrate loading/unloading position and the substrate processing position.
    Type: Application
    Filed: August 9, 2001
    Publication date: March 21, 2002
    Applicant: Hitachi Kokusai Electric, Inc.
    Inventors: Tetsuya Wada, Toshimitsu Miyata, Eisuke Nishitani
  • Publication number: 20020017363
    Abstract: A substrate processing apparatus comprises a processing chamber; a susceptor on which a substrate to be processed is to be placed; and a heating unit disposed below the susceptor for heating the substrate to be processed placed on the susceptor. The susceptor and the heating unit are accommodated in the processing chamber, and in a state in which the susceptor and the heating unit are relatively rotated, the substrate to be processed is processed. At least the susceptor is lifted and lowered in the processing chamber, and a substrate to be processed lifting and lowering apparatus for lifting and lowering the substrate to be processed with respect to at least a portion of the susceptor is disposed in the processing chamber.
    Type: Application
    Filed: March 23, 2001
    Publication date: February 14, 2002
    Inventors: Seiyo Nakashima, Michiko Nishiwaki, Yukinori Aburatani, Satoshi Okada, Eisuke Nishitani, Kazuhiro Nakagomi, Kazuhito Ikeda, Kazuhiro Shimeno, Gakuji Ohta, Katsuhisa Kasanami
  • Publication number: 20010025600
    Abstract: A substrate processing apparatus comprises a chamber, a gas introducing portion, a gas discharge port, a substrate transfer gate, and a substrate moving member which moves the substrate between a substrate processing position where the substrate is processed in the chamber and a substrate transferring in-out position in the chamber where the substrate transferred into the chamber from the substrate transfer gate is located and where the substrate is located when the substrate is transferred out from the chamber through the substrate transfer gate. The gas introducing portion, the substrate processing position, the gas discharge port and the substrate transfer gate are disposed in this order. A gas restraining member which restrains processing gas for processing the substrate from flowing toward the substrate transfer gate is provided between the gas discharge port and the substrate transfer gate.
    Type: Application
    Filed: February 9, 2001
    Publication date: October 4, 2001
    Inventors: Kazuhito Ikeda, Eisuke Nishitani, Harunobu Sakuma, Kazuhiro Nakagomi
  • Patent number: 6171641
    Abstract: A vacuum processing apparatus for performing various processes on a wafer in a vacuum chamber, and a film deposition method and a film deposition apparatus using this vacuum processing apparatus. The vacuum processing apparatus, the film deposition method and the film deposition apparatus using the vacuum processing apparatus according to this invention are characterized in that temperature control of the wafer is performed in a film deposition process, and particularly characterized in that after the emissivity calibration using a combination of a temperature calibration stage and a shutter is performed, the substrate is transferred to stages in a vacuum film deposition process chamber, and a film is deposited on the substrate by controlling the substrate temperature to a specified temperature.
    Type: Grant
    Filed: June 15, 1994
    Date of Patent: January 9, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Akira Okamoto, Shigeru Kobayashi, Hideaki Shimamura, Susumu Tsuzuku, Eisuke Nishitani, Satosi Kisimoto, Yuji Yoneoka
  • Patent number: 5815396
    Abstract: The present invention relates to vacuum processing equipment for processing a wafer in a vacuum, and film coating or forming equipment and method for forming a film on a wafer wherein radiation measurement and temperature control of the wafer is carried out by using an infrared radiation thermometer. Based upon the radiation measurement, heating and/or cooling of the wafer during processing is carried out.
    Type: Grant
    Filed: May 9, 1995
    Date of Patent: September 29, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Hideaki Shimamura, Yuji Yoneoka, Shigeru Kobayashi, Satosi Kisimoto, Sunao Matsubara, Hiroyuki Shida, Yukio Tanigaki, Masashi Yamamoto, Susumu Tsuzuku, Eisuke Nishitani, Tokio Kato, Akira Okamoto
  • Patent number: 5707500
    Abstract: The present invention relates to vacuum processing equipment for processing a wafer in a vacuum, and film coating or forming equipment and method for forming a film on a wafer wherein radiation measurement and temperature control of the wafer is carried out by using an infrared radiation thermometer. Based upon the radiation measurement, heating and/or cooling of the wafer during processing is carried out.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: January 13, 1998
    Assignee: Hitachi, Ltd
    Inventors: Hideaki Shimamura, Yuji Yoneoka, Shigeru Kobayashi, Satosi Kisimoto, Sunao Matsubara, Hiroyuki Shida, Yukio Tanigaki, Masashi Yamamoto, Susumu Tsuzuku, Eisuke Nishitani, Tokio Kato, Akira Okamoto
  • Patent number: 5670421
    Abstract: The present invention relates to a method for filling small via holes provided to insulating film on a wafer to expose parts of the underlayer of the wafer by metal by means of CVD, and an apparatus therefor. The gist of the present invention lies in that, before CVD is conducted, a surface cleaning treatment of small via hole bottom underlayer surface and a stabilization treatment of insulating film surface activated thereby are carried out successively or simultaneously and optionally an anti-corrosive treatment is applied to underlayer surface, and then the CVD treatment is conducted without exposing the underlayer metal subjected to above treatments to the air. The present invention provides an effect of enabling via filling by metal which shows good selectivity and gives a low interfacial resistance between underlayer metal and filled metal.
    Type: Grant
    Filed: January 23, 1996
    Date of Patent: September 23, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Eisuke Nishitani, Susumu Tsuzuku, Shigeru Kobayashi, Osamu Kasahara, Hiroki Nezu, Masakazu Ishino, Tsuyoshi Tamaru
  • Patent number: 5574247
    Abstract: A CVD reactor apparatus includes a substrate clamp for clamping a peripheral edge of the front of a substrate disposed in a CVD reactor and, dividing a space in the reactor into a first space adjacent the front of the substrate and a second space adjacent the backside of the substrate. The apparatus also includes a unit for cooling the surface temperature of an inner wall of the reactor to a temperature equal to or less than a deposition lower limit, and a unit for supplying a CVD gas to the first space adjacent the substrate front and supplying an inert gas to the second space adjacent the substrate backside at different pressures and causing a reaction at only the substrate front, a reaction gas monitor and a substrate temperature monitor.
    Type: Grant
    Filed: June 21, 1994
    Date of Patent: November 12, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Eisuke Nishitani, Susmu Tsuzuku, Natsuyo Chiba, Shigeru Kobayashi, Naoyuki Tamura, Norihiro Uchida
  • Patent number: 5498768
    Abstract: The present invention relates to a method for filling small via holes provided to insulating film on a wafer to expose parts of the underlayer of the wafer by metal by means of CVD, and an apparatus therefor. The gist of the present invention lies in that, before CVD is conducted, a surface cleaning treatment of small via hole bottom underlayer surface and a stabilization treatment of insulating film surface activated thereby are carried out successively or simultaneously and optionally an anti-corrosive treatment is applied to underlayer surface, and then the CVD treatment is conducted without exposing the underlayer metal subjected to above treatments to the air. The present invention provides an effect of enabling via filling by metal which shows good selectivity and gives a low interfacial resistance between underlayer metal and filled metal.
    Type: Grant
    Filed: July 6, 1993
    Date of Patent: March 12, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Eisuke Nishitani, Susumu Tsuzuku, Shigeru Kobayashi, Osamu Kasahara, Hiroki Nezu, Masakazu Ishino, Tsuyoshi Tamaru
  • Patent number: 4979466
    Abstract: An apparatus for depositing metal thin film on predetermined portions of an underlayer of a substrate by a chemical deposition method with good selectivity, good reproducibility and high deposition rate. Hydrogen atoms are prevented from adhering to portions of the substrate not to be deposited with a metal using a light source for heating only the substrate while cooling other portions exposed to starting material gases or a special gas flow controlling plate or shading plate.
    Type: Grant
    Filed: March 8, 1989
    Date of Patent: December 25, 1990
    Assignee: Hitachi, Ltd.
    Inventors: Eisuke Nishitani, Tsuzuku, Mitsuo Nakatani, Masaaki Maehara, Mitsuaki Horiuchi, Koichiro Mizukami
  • Patent number: 4830891
    Abstract: A metal thin film is deposited on predetermined portions of an underlayer of a substrate by a chemical deposition method with good selectivity, good reproducibility and high deposition rate by preventing hydrogen atoms from the adhesion to portions of the substrate not to be deposited with a metal using a special means for heating only the substrate or a special gas flow controlling means.
    Type: Grant
    Filed: November 30, 1987
    Date of Patent: May 16, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Eisuke Nishitani, Susumu Tsuzuku, Mitsuo Nakatani, Masaaki Maehara, Mitsuaki Horiuchi, Koichiro Mizukami