Patents by Inventor Elan Banin
Elan Banin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11283456Abstract: An apparatus for generating an oscillation signal is provided. The apparatus includes a first oscillator configured to generate a first reference oscillation signal, and a second oscillator configured to generate a second reference oscillation signal. A frequency accuracy of the first oscillator is higher than a frequency accuracy of the second oscillator. Further, an oscillator phase noise of the second oscillator is lower than an oscillator phase noise of the first oscillator. The apparatus further includes a processing circuit configured to generate a third reference oscillation signal based on the first reference oscillation signal and the second reference oscillation signal. Additionally, the apparatus includes a phase-locked loop configured to generate the oscillation signal based on the third reference oscillation signal. A frequency of the oscillation signal is a multiple of a frequency of the third reference oscillation signal.Type: GrantFiled: August 5, 2019Date of Patent: March 22, 2022Assignee: Intel CorporationInventors: Ofir Degani, Igal Kushnir, Elan Banin, Rotem Banin
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Publication number: 20220057480Abstract: A method and apparatus for generating a frequency-modulated continuous wave (FMCW) signal. The apparatus may include a first oscillator configured to generate a first oscillation signal, a frequency modulator configured to generate a frequency-modulated oscillation signal from the first oscillation signal based on a sequence of control words, a frequency modulation code generator configured to generate a sequence of frequency modulation codes for generating an FMCW waveform, and a frequency multiplier configured to generate the FMCW signal by up-converting the frequency-modulated oscillation signal. The sequence of control words is generated based on the sequence of frequency modulation codes. The apparatus may include a second oscillator configured to generate a second oscillation signal, and a phase detector configured to detect a phase difference between the first oscillation signal and the second oscillation signal and generate an offset code based on the phase difference.Type: ApplicationFiled: March 12, 2019Publication date: February 24, 2022Inventors: Igal KUSHNIR, Elan BANIN, Rotem BANIN, Ofir DEGANI, Ashoke RAVI
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Publication number: 20220029650Abstract: A transmitter for generating a radio frequency, RF, transmit signal is provided. The transmitter includes signal generation circuitry configured to generate, based on a sequence of first control words each indicating a respective frequency shift with respect to a target frequency of the RF transmit signal, a RF carrier signal with sequentially varying frequency over time in order to frequency spread the RF transmit signal. Further, the transmitter includes modulation circuitry configured to generate the RF transmit signal by modulating the RF carrier signal with a modulation control signal. The transmitter additionally includes modification circuitry configured to generate the modulation control signal by modifying, based on the sequence of first control words, phase information of a baseband signal bearing information to be transmitted or phase information of a signal derived from the baseband signal in order to frequency de-spread the RF transmit signal.Type: ApplicationFiled: July 23, 2020Publication date: January 27, 2022Inventors: Elan BANIN, Ofir DEGANI, Rotem BANIN, Shahar GROSS
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Publication number: 20210391853Abstract: Techniques are described related to digital radio control, partitioning, and operation. The various techniques described herein enable high-frequency local oscillator signal generation and frequency multiplication using radio-frequency (RF) digital to analog converters (RFDACs). The use of these components and others described throughout this disclosure allow for the realization of various improvements. For example, digital, analog, and hybrid beamforming control are implemented and the newly-enabled digital radio architecture partitioning enables radio components to be pushed to the radio head, allowing for the omission of high frequency cables and/or connectors.Type: ApplicationFiled: December 28, 2018Publication date: December 16, 2021Inventors: Benjamin Jann, Ashoke Ravi, Satwik Patnaik, Elan Banin, Ofir Degani, Nebil Tanzi, Brandon Davis, Igal Kushnir, Jonathan Jensen, Sidharth Dalmia, Peter Pawliuk
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Publication number: 20210367629Abstract: Techniques are described related to digital radio control and operation. The various techniques described herein enable high-frequency local oscillator (LO) signal generation using injection locked cock multipliers (ILCMs). The techniques also include the use of LO signals for carrier aggregation applications for phased array front ends. Furthermore, the disclosed techniques include the use of array element-level control using per-chain DC-DC converters. Still further, the disclosed techniques include the use of adaptive spatial filtering and optimal combining of analog-to-digital converters (ADCs) to maximize dynamic range in digital beamforming systems.Type: ApplicationFiled: August 4, 2021Publication date: November 25, 2021Inventors: Ashoke Ravi, Benjamin Jann, Satwik Patnaik, Alexandros Margomenos, Igal Kushnir, Elan Banin, Ofir Degani
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Patent number: 11121731Abstract: Techniques are described related to digital radio control and operation. The various techniques described herein enable high-frequency local oscillator (LO) signal generation using injection locked cock multipliers (ILCMs). The techniques also include the use of LO signals for carrier aggregation applications for phased array front ends. Furthermore, the disclosed techniques include the use of array element-level control using per-chain DC-DC converters. Still further, the disclosed techniques include the use of adaptive spatial filtering and optimal combining of analog-to-digital converters (ADCs) to maximize dynamic range in digital beamforming systems.Type: GrantFiled: August 26, 2019Date of Patent: September 14, 2021Assignee: Intel CorporationInventors: Ashoke Ravi, Benjamin Jann, Satwik Patnaik, Elan Banin, Igal Kushnir, Ofir Degani, Alexandros Margomenos
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Publication number: 20210265999Abstract: An apparatus for generating an oscillation signal is provided. The apparatus includes a first oscillator configured to generate a first reference oscillation signal, and a second oscillator configured to generate a second reference oscillation signal. A frequency accuracy of the first oscillator is higher than a frequency accuracy of the second oscillator. Further, an oscillator phase noise of the second oscillator is lower than an oscillator phase noise of the first oscillator. The apparatus further includes a processing circuit configured to generate a third reference oscillation signal based on the first reference oscillation signal and the second reference oscillation signal. Additionally, the apparatus includes a phase-locked loop configured to generate the oscillation signal based on the third reference oscillation signal. A frequency of the oscillation signal is a multiple of a frequency of the third reference oscillation signal.Type: ApplicationFiled: August 5, 2019Publication date: August 26, 2021Inventors: Ofir DEGANI, Igal KUSHNIR, Elan BANIN, Rotem BANIN
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Patent number: 11095427Abstract: A transceiver, including a modulation circuit configured to modulate a first digital word into a first modulated time signal; and a demodulation circuit configured to demodulate a second modulated time signal into a second digital word, wherein the modulation and demodulation circuits are operable without an external clock source, and inseparably share one or more same circuit elements. Also, a tunable delay line may be configured to set a time rate of the modulation, wherein the modulation circuit and the demodulation circuit inseparably share the tunable delay line.Type: GrantFiled: September 25, 2020Date of Patent: August 17, 2021Assignee: Intel CorporationInventors: Rotem Banin, Elan Banin, Ofir Degani, Ronen Gernizky, Ashoke Ravi
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Patent number: 11088891Abstract: A communication circuitry device for correcting a phase imbalance, the communication circuitry device comprising one or more processors configured to estimate a non-linear component of a reference signal based on a measurement of a tone at a first harmonic of a plurality of harmonics of the reference signal, estimate an in-phase component of the reference signal based on subtracting the non-linear component from a measurement of a tone at a second harmonic of the plurality of harmonics of the reference signal, and generate a calibration signal based on the estimation of the in-phase component.Type: GrantFiled: March 26, 2020Date of Patent: August 10, 2021Assignee: Intel CorporationInventors: Elan Banin, Ran Shimon, Shahar Gross, Nurit Spingarn
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Publication number: 20210199511Abstract: A device may comprise: a storage for storing a reference output representing an output of an electrical circuit at a reference temperature; one or more processors, configured to: determine a temperature shift based on a comparison of an output of the electrical circuit sensed at a sensing temperature and the reference output; determine a plurality of coefficients of a model of the temperature shift, wherein the model implements one or more functions that associate the plurality of coefficients and a temperature with the temperature shift at the temperature.Type: ApplicationFiled: December 27, 2019Publication date: July 1, 2021Inventors: Omer SHOLEV, Elan BANIN, Ofir DEGANI, Assaf BEN-BASSAT
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Publication number: 20210112371Abstract: Among other things, embodiments of the present disclosure help to overcome environment-specific dependency issues of conventional Wi-Fi-based sensing systems, thus allowing a neural network to make better proximity predictions in an unseen environment. Other embodiments may be described and claimed.Type: ApplicationFiled: December 21, 2020Publication date: April 15, 2021Inventors: Omer Sholev, Ofir Degani, Elan Banin, Uri Parker, Assaf Gurevitz
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Publication number: 20210067182Abstract: Techniques are described related to digital radio control and operation. The various techniques described herein enable high-frequency local oscillator (LO) signal generation using injection locked cock multipliers (ILCMs). The techniques also include the use of LO signals for carrier aggregation applications for phased array front ends. Furthermore, the disclosed techniques include the use of array element-level control using per-chain DC-DC converters. Still further, the disclosed techniques include the use of adaptive spatial filtering and optimal combining of analog-to-digital converters (ADCs) to maximize dynamic range in digital beamforming systems.Type: ApplicationFiled: August 26, 2019Publication date: March 4, 2021Inventors: Ashoke Ravi, Jann Benjamin, Satwik Patnaik, Elan Banin, Igal Kushnir, Ofir Degani, Alexandros Margomenos
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Patent number: 10788794Abstract: A digital to time converter (DTC) system is disclosed. The DTC system comprises a DTC circuit configured to generate a DTC output clock signal at a DTC output frequency, based on a DTC code. In some embodiments, the DTC system further comprises a calibration circuit comprising a period error determination circuit configured to determine a plurality of period errors respectively associated with a plurality consecutive edges of the DTC output clock signal. In some embodiments, each period error of the plurality of period errors comprises a difference in a measured time period between two consecutive edges of the DTC output clock signal from a predefined time period. In some embodiments, the calibration circuit further comprises an integral non-linearity (INL) correction circuit configured to determine a correction to be applied to the DTC code based on a subset of the determined period errors.Type: GrantFiled: September 9, 2019Date of Patent: September 29, 2020Assignee: Intel CorporationInventors: Ofir Degani, Elan Banin, Eran Ben Ami
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Patent number: 10768580Abstract: A time-to-digital converter is provided. The time-to-digital converter includes a delay circuit configured to iteratively delay a reference signal for generating a plurality of delayed reference signals. Further, the time-to-digital converter includes a plurality of sample circuits each configured to sample an oscillation signal based on one of the plurality of delayed reference signals. The time-to-digital converter additionally includes a control circuit configured to de-activate at least one of the plurality of sample circuits based on a predicted value of the phase of the oscillation signal.Type: GrantFiled: March 2, 2017Date of Patent: September 8, 2020Assignee: Intel IP CorporationInventors: Yair Dgani, Michael Kerner, Elan Banin, Evgeny Shumaker, Gil Horovitz, Ofir Degani, Rotem Banin, Aryeh Farber, Rotem Avivi, Eshel Gordon, Tami Sela
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Patent number: 10707880Abstract: A circuit is configured to reduce a noise component of a measured phase signal. The circuit includes an input for a phase signal of an oscillator and an error signal estimator configured to determine parity information and an estimated error amplitude in the phase signal based on the parity information. The circuit further includes a combiner configured to provide the measured phase signal with the reduced noise component based on a combination of the phase signal and the estimated error amplitude.Type: GrantFiled: January 24, 2017Date of Patent: July 7, 2020Assignee: Intel IP CorporationInventors: Elan Banin, Tamar Marom, Gil Horovitz, Rotem Banin
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Publication number: 20200212943Abstract: An apparatus for generating a data signal comprises a processing circuit configured to generate the data signal, the data signal comprising a sequence of a first signal edge of a first type, a second signal edge of a second type, and a third signal edge of the first type, the first signal edge and the second signal edge being separated by a first time period corresponding to first data to be transmitted, and the second signal edge and the third signal edge being separated by a second time period corresponding to second data to be transmitted. An output interface circuit is configured to output the data signal.Type: ApplicationFiled: September 17, 2018Publication date: July 2, 2020Inventors: Elan Banin, Eytan Mann, Rotem Banin, Ronen Gernizky, Ofir Degani, Igal Kushnir, Shahar Porat, Amir Rubin, Vladimir Volokitin, Elinor Kashani, Dmitry Felsenstein, Ayal Eshkoli, Tal Davidson, Eng Hun Ooi, Yossi Tsfati, Ran Shimon
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Patent number: 10686451Abstract: Aspects of a digital phase-lock loop (DPLL) with an adjustable delay between an output clock and a reference clock in accordance with phase noise compensation are generally described herein. An apparatus may include processing circuitry configured to, in a first mode, identify a delay element of a plurality of delay elements based on an associated delay value, and set an initial phase difference value to a phase difference value associated with the identified delay element. The processor circuitry may be further configured to, in a second mode, in a second mode, initialize the DPLL using the initial phase difference value, determine a phase error between a reference clock and a feedback clock based on the initial phase difference value, adjust an output clock signal based on the phase error.Type: GrantFiled: December 30, 2016Date of Patent: June 16, 2020Assignee: Apple Inc.Inventors: Yair Dgani, Michael Kerner, Elan Banin, Nati Dinur, Gil Horovitz, Rotem Banin
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Patent number: 10680619Abstract: A Digital Phase Locked Loop (DPLL), including a Time-to-Digital Converter (TDC) configured generate quantized phase values of a controlled oscillator signal; and a frequency estimation circuit configured to receive the quantized phase values, determine wraparound phase of the quantized phase values, and estimate a frequency based on the quantized phase values and the wraparound phase.Type: GrantFiled: October 25, 2018Date of Patent: June 9, 2020Assignee: Intel IP CorporationInventors: Elan Banin, Roy Amel, Ran Shimon, Ashoke Ravi, Nati Dinur
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Patent number: 10659061Abstract: A divider-less fractional digital phase locked loop (PLL) is disclosed and can include a time-to-digital converter (TDC) to receive a reference clock signal and a digitally control oscillator (DCO) clock signal, and generate a phase difference signal based on the reference clock signal and the DCO clock signal. A counter coupled in parallel to the TDC can receive the clock signal and count an output frequency of the clock signal to detect reference noise within the reference signal that is above a threshold. A sampler can sample an output of the counter using a replica of the reference signal, and generate a plurality of samples. A sample selector can select one of the plurality of samples based on the phase difference signal. A digital phase detector (DPD) can generate an output phase measurement based on the phase difference signal and the selected sample of the plurality of samples.Type: GrantFiled: December 27, 2016Date of Patent: May 19, 2020Assignee: Intel CorporationInventors: Elias Nassar, Eyal Fayneh, Inbar Falkov, Elan Banin, Rotem Banin, Ofir Degani, Samer Nassar
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Publication number: 20200067513Abstract: Aspects of a digital phase-lock loop (DPLL) with an adjustable delay between an output clock and a reference clock in accordance with phase noise compensation are generally described herein. An apparatus may include processing circuitry configured to, in a first mode, identify a delay element of a plurality of delay elements based on an associated delay value, and set an initial phase difference value to a phase difference value associated with the identified delay element. The processor circuitry may be further configured to, in a second mode, in a second mode, initialize the DPLL using the initial phase difference value, determine a phase error between a reference clock and a feedback clock based on the initial phase difference value, adjust an output clock signal based on the phase error.Type: ApplicationFiled: December 30, 2016Publication date: February 27, 2020Inventors: YAIR DGANI, Michael Kerner, Elan Banin, Nati Dinur, Gil Horovitz, Rotem Banin