Abstract: Described herein are technologies related to an implementation of a divider-less digital phase-locked loop (DPLL) that includes a loop response matching a higher order sigma delta.

Abstract: Logic for direct current (DC) estimation of a wireless communication packet. Logic may determine a first DC estimation based upon a first set of sequences in a preamble of the wireless communication packet. Logic may determine a second DC estimation based upon a second set of sequences in the preamble. Logic may select one of the DC estimations based upon a frequency-offset estimation. Logic may remove one of the DC estimations from the packet. Logic to null DC bins that result from a Fourier transform of the packet to mitigate transmitter DC bias. And logic to determine a correction for the packet based upon a difference between a predetermined guard interval value and a received guard interval value and to apply the correction to the packet.

Abstract: Some demonstrative embodiments include apparatuses, systems and/or methods of In-phase/Quadrature (I/Q) imbalance compensation. For example, an apparatus may include an I/Q imbalance calibrator to determine, based on first and second phasors, a plurality of calibration parameters for calibrating I/Q imbalance of both a Radio Frequency (RF) Receive (Rx) path of a transceiver and a RF Transmit (Tx) path of the transceiver, the first phasor including a phasor of an image component of a first signal transmitted via the Tx path, shifted by a first phase shift and received via the Rx path, and the second phasor including a phasor of an image component of a second signal transmitted via the Tx path, shifted by a second phase shift, different from the first phase shift, and received via the Rx path.

Abstract: Some demonstrative embodiments include apparatuses, systems and/or methods of In-phase/Quadrature (I/Q) imbalance compensation. For example, an apparatus may include an I/Q imbalance calibrator to determine, based on first and second phasors, a plurality of calibration parameters for calibrating I/Q imbalance of both a Radio Frequency (RF) Receive (Rx) path of a transceiver and a RF Transmit (Tx) path of the transceiver, the first phasor including a phasor of an image component of a first signal transmitted via the Tx path, shifted by a first phase shift and received via the Rx path, and the second phasor including a phasor of an image component of a second signal transmitted via the Tx path, shifted by a second phase shift, different from the first phase shift, and received via the Rx path.

Abstract: Some demonstrative embodiments include devices, systems and/or methods of Direct Current (DC) estimation. For example, an apparatus may include an estimator to estimate a DC component of a received wireless communication packet based on a first value, a second value and an estimated frequency offset, wherein the first value is based on a first plurality of samples including at least a plurality of samples of a first sequence of a preamble of the wireless communication packet, the second value is based on a second plurality of samples including at least a plurality of samples of a second sequence of the preamble, immediately successive to the first sequence, and the estimated frequency offset corresponds to a frequency offset between the first and second pluralities of samples.