Abstract: A digital to time converter (DTC) system is disclosed. The DTC system comprises a DTC circuit configured to generate a DTC output clock signal at a DTC output frequency, based on a DTC code. In some embodiments, the DTC system further comprises a calibration circuit comprising a period error determination circuit configured to determine a plurality of period errors respectively associated with a plurality consecutive edges of the DTC output clock signal. In some embodiments, each period error of the plurality of period errors comprises a difference in a measured time period between two consecutive edges of the DTC output clock signal from a predefined time period. In some embodiments, the calibration circuit further comprises an integral non-linearity (INL) correction circuit configured to determine a correction to be applied to the DTC code based on a subset of the determined period errors.

Abstract: A time-to-digital converter is provided. The time-to-digital converter includes a delay circuit configured to iteratively delay a reference signal for generating a plurality of delayed reference signals. Further, the time-to-digital converter includes a plurality of sample circuits each configured to sample an oscillation signal based on one of the plurality of delayed reference signals. The time-to-digital converter additionally includes a control circuit configured to de-activate at least one of the plurality of sample circuits based on a predicted value of the phase of the oscillation signal.

Abstract: A divider-less fractional digital phase locked loop (PLL) is disclosed and can include a time-to-digital converter (TDC) to receive a reference clock signal and a digitally control oscillator (DCO) clock signal, and generate a phase difference signal based on the reference clock signal and the DCO clock signal. A counter coupled in parallel to the TDC can receive the clock signal and count an output frequency of the clock signal to detect reference noise within the reference signal that is above a threshold. A sampler can sample an output of the counter using a replica of the reference signal, and generate a plurality of samples. A sample selector can select one of the plurality of samples based on the phase difference signal. A digital phase detector (DPD) can generate an output phase measurement based on the phase difference signal and the selected sample of the plurality of samples.

Abstract: A digital to time converter (DTC) system is disclosed. The DTC system comprises a DTC circuit configured to generate a DTC output clock signal at a DTC output frequency, based on a DTC code. In some embodiments, the DTC system further comprises a calibration circuit comprising a period error determination circuit configured to determine a plurality of period errors respectively associated with a plurality consecutive edges of the DTC output clock signal. In some embodiments, each period error of the plurality of period errors comprises a difference in a measured time period between two consecutive edges of the DTC output clock signal from a predefined time period. In some embodiments, the calibration circuit further comprises an integral non-linearity (INL) correction circuit configured to determine a correction to be applied to the DTC code based on a subset of the determined period errors.

Abstract: Systems, methods, and circuitries for synchronizing a first phase locked loop (PLL) with a second PLL are provided. In one example a PLL system includes a first PLL configured to generate a first signal; a second PLL configured to generate a second signal; and phase calculation circuitry. The phase calculation circuitry is configured to calculate a phase of the first signal at a given time; and provide the calculated phase to the second PLL for use by the second PLL in synchronizing a phase of the second with the phase of the first signal.

Abstract: A Digital Phase Locked Loop (DPLL), including a Time-to-Digital Converter (TDC) configured generate quantized phase values of a controlled oscillator signal; and a frequency estimation circuit configured to receive the quantized phase values, determine wraparound phase of the quantized phase values, and estimate a frequency based on the quantized phase values and the wraparound phase.

Abstract: A circuit is configured to reduce a noise component of a measured phase signal. The circuit includes an input for a phase signal of an oscillator and an error signal estimator configured to determine parity information and an estimated error amplitude in the phase signal based on the parity information. The circuit further includes a combiner configured to provide the measured phase signal with the reduced noise component based on a combination of the phase signal and the estimated error amplitude.

Abstract: A Digital Phase Locked Loop (DPLL), including a Time-to-Digital Converter (TDC) configured generate quantized phase values of a Voltage Controlled Oscillator (VCO) signal; and a frequency estimation circuit configured to receive the quantized phase values, determine wraparound phase of the quantized phase values, and least-squares estimate a frequency based on the quantized phase values and the wraparound phase.

Abstract: Systems, methods, and circuitries for synchronizing a first phase locked loop (PLL) with a second PLL are provided. In one example a PLL system includes a first PLL configured to generate a first signal; a second PLL configured to generate a second signal; and phase calculation circuitry. The phase calculation circuitry is configured to calculate a phase of the first signal at a given time; and provide the calculated phase to the second PLL for use by the second PLL in synchronizing a phase of the second with the phase of the first signal.

Abstract: Devices and methods of compensating for a bandpass filter are generally described. A DTx includes a BPF from which an output signal is produced and a DFE having a zero crossing (ZC) pre-distorter (ZCPD). The ZCPD compensates for ZC distortion from a desired analog signal caused by the BPF. The ZCPD adjusts a DTC code word to generate a DTx output signal to be applied to the BPF. The compensation is dependent on a magnitude of the square wave immediately prior to and after the ZC. The compensated DTC and a DPA code word are used to generate the DTx output signal. The compensation produced by the ZCPD is free from compensation for non-linear responses to the DTC and DPA code words.

Abstract: A Digital Phase Locked Loop (DPLL), including a Time-to-Digital Converter (TDC) configured generate quantized phase values of a Voltage Controlled Oscillator (VCO) signal; and a frequency estimation circuit configured to receive the quantized phase values, determine wraparound phase of the quantized phase values, and least-squares estimate a frequency based on the quantized phase values and the wraparound phase.

Abstract: Devices and methods of compensating for a bandpass filter are generally described. A DTx includes a BPF from which an output signal is produced and a DFE having a zero crossing (ZC) pre-distorter (ZCPD). The ZCPD compensates for ZC distortion from a desired analog signal caused by the BPF. The ZCPD adjusts a DTC code word to generate a DTx output signal to be applied to the BPF. The compensation is dependent on a magnitude of the square wave immediately prior to and after the ZC. The compensated DTC and a DPA code word are used to generate the DTx output signal. The compensation produced by the ZCPD is free from compensation for non-linear responses to the DTC and DPA code words.

Abstract: A digital phase lock loop (DPLL) device or system can operate to analyze and estimate a deterministic jitter in the digital domain, while correcting for it in the analog domain. A reference oscillator can provide an analog reference signal to the DPLL via a reference path. A shaper of the reference path can process the analog reference signal and provide a digital signal to a doubler component that doubles the frequency for a digital reference signal. The doubler component itself can add deterministic jitter to the noise of the digital reference signal it provides to the DPLL. An estimation of the DPLL performs various calibration processes to determine the deterministic jitter in the digital domain and provide an analog bias signal to the signal shaper component to correct for the deterministic jitter, keeping it at around zero.

Abstract: A digital polar transmitter arrangement having a digital front end (DFE) and a transmit chain is disclosed. The DFE is configured to resample a baseband signal relative to a carrier frequency at a carrier frequency related sample rate, calculate zero crossing positions of the resampled signal, generate delay to time converter (DTC) commands based on the zero crossing positions, calculate amplitude values for the zero crossing positions and generate dynamic phase alignment (DPA) commands based on the amplitude values. The transmit chain is configured to generate an output signal having amplitude and phase modulation based on the DTC and DPA commands.

Abstract: Logic for spur estimation of a wireless communication packet. Logic may receive an input signal output by a set of analog-to-digital converters and determine means of sequences for each of the analog-to-digital converters. The sequences may be from a preamble of the wireless communication packet. The sequences may comprise a set of short training sequences with an average zero mean received after logic detects a boundary of the sequences. The set of short training sequences may comprise a Golay sequence Ga and a Golay sequence ?Ga. Logic may determine spur estimations for each of the analog-to-digital converters based upon a frequency offset estimation for the wireless communication packet. Logic may remove a mean of the spur estimations from the spur estimations. And logic may remove the spur estimations from the packet.

Abstract: Described herein are technologies related to an implementation of a divider-less digital phase-locked loop (DPLL) that includes a loop response matching a higher order sigma delta.

Abstract: Logic for spur estimation of a wireless communication packet. Logic may receive an input signal output by a set of analog-to-digital converters and determine means of sequences for each of the analog-to-digital converters. The sequences may be from a preamble of the wireless communication packet. The sequences may comprise a set of short training sequences with an average zero mean received after logic detects a boundary of the sequences. The set of short training sequences may comprise a Golay sequence Ga and a Golay sequence ?Ga. Logic may determine spur estimations for each of the analog-to-digital converters based upon a frequency offset estimation for the wireless communication packet. Logic may remove a mean of the spur estimations from the spur estimations. And logic may remove the spur estimations from the packet.

Abstract: Some demonstrative embodiments include devices, systems and/or methods of Direct Current (DC) estimation. For example, an apparatus may include an estimator to estimate a DC component of a received wireless communication packet based on a first value, a second value and an estimated frequency offset, wherein the first value is based on a first plurality of samples including at least a plurality of samples of a first sequence of a preamble of the wireless communication packet, the second value is based on a second plurality of samples including at least a plurality of samples of a second sequence of the preamble, immediately successive to the first sequence, and the estimated frequency offset corresponds to a frequency offset between the first and second pluralities of samples.

Abstract: Logic for direct current (DC) estimation of a wireless communication packet. Logic may determine a first DC estimation based upon a first set of sequences in a preamble of the wireless communication packet. Logic may determine a second DC estimation based upon a second set of sequences in the preamble. Logic may select one of the DC estimations based upon a frequency-offset estimation. Logic may remove one of the DC estimations from the packet. Logic to null DC bins that result from a Fourier transform of the packet to mitigate transmitter DC bias. And logic to determine a correction for the packet based upon a difference between a predetermined guard interval value and a received guard interval value and to apply the correction to the packet.

Abstract: A digital phase locked loop operates with a time-to-digital converter and an a-priori-probability-phase-estimation component or estimator component that estimates the un-quantized phase associated with a quantization output of the time-to-digital converter. The time-to-digital converter generates a quantized value as the quantization output from a local oscillator signal of a local oscillator and a reference signal of a reference clock. The estimation component estimates a phase value from the quantized values as a function of a-priori data related to the time-to-digital converter and boundaries of the quantized value.