Abstract: A MEMS resonant sensor adapted to generate a pulse output signal from a signal of interest, the signal of interest being a signal having a frequency oscillating around a carrier frequency, the MEMS sensor comprising at least one processing channel for processing the signal of interest, each processing channel comprising: a demodulation unit for demodulating the signal of interest in order to form a demodulated signal, the demodulation unit comprising a frequency mixer between the signal of interest and a reference signal, the demodulated signal having a low-frequency component and a high-frequency component; a filtration unit for filtering the demodulated signal in order to form a filtered signal, the filtration unit being adapted to allow through the low-frequency component of the demodulated signal; a comparison unit for comparing the filtered signal with a fixed threshold signal in order to form a comparison signal, the comparison signal comprising rising edges and falling edges; a detection unit for detec

Abstract: The present disclosure relates to a neural network comprising a first synapse circuit (106) configured to apply a first time delay to a first input signal (READ1) using a first resistive memory element (108) and to generate a first output signal at an output of the first synapse circuit by applying a first weight to the delayed first input signal; and a second synapse circuit (106) configured to apply a second time delay, different to the first time delay, to the first input signal, or to a second input signal (READN), using a second resistive memory element (108) and to generate a second output signal at an output of the second synapse circuit by applying a second weight to the delayed second input signal.

Abstract: A data storage circuit includes a first memory array comprising a plurality of FeRAM memory units; a second memory array comprising a plurality of OxRAM memory units; each of the first and second memory arrays comprising: a plurality of word lines, a plurality of source lines and a plurality of bit lines; for each column each memory unit comprising: a memory cell having a first electrode and a second electrode connected to the source line associated to the memory unit; a selection transistor having a gate connected to the word line associated to the memory unit and placed in series with the memory cell between the source line and a bit line associated to of the memory unit; the data storage circuit comprising further: a data transfer stage configured to transfer data from a set of source FeRAM memory units having a common bit line to a target OxRAM unit by converting a read signal from the common bit line to a transfer voltage applied on a target line of the target OxRAM unit; the target line corresponding to

Abstract: A processing system for processing signals from a plurality of transducers of an ultrasonic sensor in order to determine characteristic information relating to an object detected by the ultrasonic sensor is provided. The system comprises a coupling device for transforming the signals received from the transducers into pulses, and a pulse processing unit for determining the characteristic information based on the pulses delivered by the coupling device. The coupling device comprises: a thresholding unit for applying, for each signal received from a transducer, thresholding to a signal derived from the signal received from the transducer and extracting directional information contained in the phase of the derived signal; a transformation unit for transforming the derived signal into pulses containing the phase of the signal, using the information extracted by the thresholding unit.

Abstract: A method for calculating a MAC operation is performed by a memory, in particular in the neuromorphic calculation field. It allows performing the scalar product between an activation vector whose elements are binary with a vector of synaptic coefficients, quantised over M>2 levels. The calculation comprises a first phase, in which M?1 reading voltages Vread2, . . . , VreadM-1 are applied to the word lines corresponding to a positive activation and the number of passing cells in a bit line is determined for each of these voltages. In a second phase, these M?1 reading voltages are applied to the word lines corresponding to a negative activation and, for each of them, the number of passing cells in the bit line is determined again. The scalar product is then deduced from the difference between the total number of passing cells in the first phase and the total number of passing cells in the second phase.

Abstract: A memory cell, includes first and second main terminals, an auxiliary terminal; M memristor(s) between the main terminals, M?1; M primary switch(es), each in parallel with a memristor; and a secondary switch between the second main terminal and the auxiliary terminal. It is configured for writing to at least one memristor by opening each primary switch in parallel with the at least one memristor, closing each other primary switch, closing the secondary switch and applying a corresponding programming voltage between the first main terminal and the auxiliary terminal; and for reading at least one memristor by opening each primary switch in parallel with the at least one memristor, closing each other possible primary switch, opening the secondary switch and measuring a corresponding electrical quantity between the main terminals.

Abstract: The present invention concerns a method for programming a Bayesian neural network (BNN) in a RRAM memory. After the BNN has been trained on a dataset D, the joint posterior probability distribution of the synaptic coefficients, p(w|D) is decomposed into a mixture of multivariate mean-field Gaussian components by GMM. The weighting coefficients and the parameters of these multivariate Gaussian components are estimated by MDEM (Multi-Dimensional Expectation Maximization) with two constraints. According to the first constraint, the off-diagonal terms of the covariance matrix of each component are forced to zero. According to the second constraint, the couples of mean values and diagonal terms of the covariance matrix of each component are constrained to belong to a hardware compliance domain determined by a relationship between the conductance mean value and conductance standard deviation of a memristor programmed by a SET or RESET operation.

Abstract: A data storage circuit includes a matrix array of memory cells. The memory cells are configurable and non-volatile. Each one is intended to operate in either one of two operating configurations; the first operating configuration corresponding to a ferroelectric random-access memory; and the second operating configuration corresponding to a metal-oxide resistive random-access memory. Each memory cell comprises: a stack of thin layers in the following order: a first layer made of an electrically conductive material forming a lower electrode, a second layer made of a dielectric and ferroelectric material and a third layer made of electrically conductive material forming an upper electrode.

Abstract: A computer for executing a computation algorithm involving a digital variable as per at least two operating phases is provided. The computer includes a memory stage having: a first set of memories for storing a first sub-word of each digital variable; with each memory of the first set being non-volatile and having a first read endurance and a first write cyclability; a second set of memories for storing a second sub-word of each digital variable; with each memory of the second set having a second read endurance and a second write cyclability; with the first read endurance being greater than the second read endurance and the first write cyclability being less than the second write cyclability.

Abstract: A method for co-manufacturing a FeRAM and an OxRAM includes depositing a layer of first electrode carried out identically for a zone Z1 and a zone Z2; depositing a layer of hafnium dioxide-based active material carried out identically for Z1 and Z2; depositing a first conductive layer carried out identically for Z1 and Z2; making a mask at Z2, leaving Z1 free; removing the layer at Z1, with Z2 being protected by the mask; removing the mask at Z2; and depositing a second conductive layer in contact with the layer at Z2 and in contact with the layer at Z1, the material of the layer being chosen to create oxygen vacancies in the active layer and depositing a third conductive layer carried out identically for Z1 and Z2.

Abstract: Circuit and method for controlling a resistive memory formed by resistive memory cells each provided with a resistive memory element associated in series with a selector, each cell implementing a coding referred to as “multi-level” coding and being programmed in a given programming state among k (with k>2) possible programming states, wherein during a read operation, a sequence of different read voltages are applied to the given cell, and at each applied read voltage it is detected whether the read current passing through said given cell consecutively to the application of said read voltage corresponds to a leakage current level of the selector when this selector is in an off state or to a current level when the selector is in an on state.

Abstract: A modulation device includes at least one memristive device, and a control block, the modulation device having an equivalent conductance yi(t) produced by the at least one memristive device and the control block being configured to receive a clock signal and perform a first modification of the equivalent conductance yi(t) upon receipt of each clock signal, receive an input voltage pulse and perform a second modification of the equivalent conductance yi(t) upon receipt of each input voltage pulse, the first and second modifications being in opposite directions.

Abstract: This method for training a binarized neural network, also called BNN, including neurons, with a binary weight for each connection between two neurons, is implemented by an electronic circuit and comprises: a forward pass including calculating an output vector by applying the BNN on an input vector; a backward pass including computing an error vector from the calculated output vector, and calculating a new value of the input vector by applying the BNN on the error vector; a weight update including computing a product by multiplying an element of the error vector with one of the new value of the input vector, modifying a latent variable depending on the product; and updating the weight with the latent variable; each weight being encoded using a primary memory component; each latent variable being encoded using a secondary memory component having a characteristic subject to a time drift.

Abstract: The present disclosure relates to a synapse circuit of a neural network for performing TD-lambda temporal difference learning, the neural network approximating a value function, the synapse circuit comprising: a first resistive memory device (506); a second resistive memory device (516); and a synapse control circuit (528) configured to update a synaptic weight (g?) of the synapse circuit by programming a resistive state of the first resistive memory device (506) based on a programmed conductance of the second resistive memory device (516).

Abstract: A method of producing a recurrent neural network computer includes consecutive steps of providing a substrate with a first electrode; structuring the first electrode by etching using a first mask made of block copolymers, such that said electrode has free regions which are randomly spatially distributed; forming a resistive-RAM-type memory layer on the first structured electrode; forming a second electrode on the memory layer; and structuring the second electrode by etching, using a second mask made of block copolymers such that said electrode has free regions which are randomly spatially distributed.

Abstract: A processing system for processing signals from a plurality of transducers of an ultrasonic sensor in order to determine characteristic information relating to an object detected by the ultrasonic sensor is provided. The system comprises a coupling device for transforming the signals received from the transducers into pulses, and a pulse processing unit for determining the characteristic information based on the pulses delivered by the coupling device. The coupling device comprises: a thresholding unit for applying, for each signal received from a transducer, thresholding to a signal derived from the signal received from the transducer and extracting directional information contained in the phase of the derived signal; a transformation unit for transforming the derived signal into pulses containing the phase of the signal, using the information extracted by the thresholding unit.

Abstract: A method for unsupervised sorting, in real time, of action potentials of biological neurons by a network of artificial neurons including input, intermediate and output layers, the method according to which: the input layer receives an electrical signal measuring an electrical activity of biological neurons, the electrical signal having a variable amplitude as a function of action potentials emitted by the plurality of biological neurons over time; the input layer converts the amplitude of the electrical signal into a train of first spikes; the input layer transmits the train of first spikes to the intermediate layer; the intermediate layer converts the train of first spikes into a train of second spikes; the intermediate layer transmits the train of second spikes to the output layer; as a function of the train of second spikes, the output layer sorts each occurrence of each type of action potential present in the electrical signal.

Abstract: The present disclosure relates to a neuron circuit of a spiking neural network comprising: a first resistive switching memory device having a conductance that decays over time; and a programming circuit configured to reset the resistive state of the first resistive switching element in response to a spike in an output voltage of the neuron circuit.

Abstract: The present disclosure relates to a synapse circuit of a spiking neural network comprising: at least one resistive switching memory device having a conductance that decays over time; and at least one programming circuit configured to store an eligibility trace by programming a resistive state of the at least one resistive memory device.

Abstract: The present disclosure relates to a memory circuit comprising: a transistor layer; a plurality of first memory elements positioned in a first level above the transistor layer; and a plurality of filament switching resistive memory elements positioned in a second level higher than the first level.