Abstract: A Bayesian neural network including an input layer, and, an output layer, and, possibly, one or more hidden layer(s). Each neuron of a layer is connected at its input with a plurality of synapses, the synapses of the plurality being implemented as a RRAM array constituted of cells, each column of the array being associated with a synapse and each row of the array being associated with an instance of the set of synaptic coefficients, the cells of a row of the RRAM being programmed during a SET operation with respective programming current intensities, the programming intensity of a cell being derived from the median value of a Gaussian component obtained by GMM decomposition into Gaussian components of the marginal posterior probability of the corresponding synaptic coefficient, once the BNN model has been trained on a training dataset.

Abstract: An electrochemical storage device includes an ionic transistor and an ionic capacitor, the ionic transistor including a gate electrode, the ionic capacitor including two electrodes, the device further including a connection element able to connect the gate electrode of the ionic transistor to a first of both electrodes of the ionic capacitor.

Abstract: An electrochemical charge storage device includes an ionic transistor and an ionic capacitor, the ionic transistor including a reservoir layer forming an ion reservoir; a source electrode in contact with a part of the reservoir layer; a drain electrode in contact with another part of the reservoir layer, the drain electrode and the source electrode being physically separated from each other, the source electrode and the drain electrode each being made of an electrically conductive material; and a gate electrode of an electrically conductive material, the gate electrode being separated from the reservoir layer by an ionic conductive layer of an ionic conductive and dielectric material, the ionic conductive layer being in contact with the source electrode and with the drain electrode. The ionic capacitor includes two electrodes. The ionic capacitor includes an ionic conductive layer separating the two electrodes from the ionic capacitor.

Abstract: The present disclosure relates to a routing circuit for routing signals between neuron circuits of an artificial neural network, the routing circuit comprising: a first memory cell (302) having an input coupled to a first input line (304) of the routing circuit and an output coupled to a first column line (308); a second memory cell (302) having an input coupled to a second input line (304) of the routing circuit and an output coupled to the first column line (308); and a first comparator circuit (310) configured to compare a signal (IREAD1) on the first column line (308) with a reference level, and to selectively assert a signal (VOUT1) on a first output line (312) of the routing circuit based on the comparison.

Abstract: The present disclosure relates to a memory circuit comprising: a transistor layer; a plurality of first memory elements positioned in a first level above the transistor layer; and a plurality of filament switching resistive memory elements positioned in a second level higher than the first level.

Abstract: A method for training a logistic regression classifier on a dataset by using a resistive RAM as hardware accelerator, each row of the resistive RAM including cells which can be programmed in a first resistance state or a second resistance state. The probability of a data element belonging to a class is modelled by a logistic function applied to a score of the element, where is a parameter vector of the model. The logistic regression classifier is trained by populating the resistive RAM with samples of a model parameter vector which are obtained by MCMC sampling. Once populated, the resistive RAM can be used for classifying new data.

Abstract: The present disclosure relates to a neural network comprising a first synapse circuit (106) configured to apply a first time delay to a first input signal (READ1) using a first resistive memory element (108) and to generate a first output signal at an output of the first synapse circuit by applying a first weight to the delayed first input signal; and a second synapse circuit (106) configured to apply a second time delay, different to the first time delay, to the first input signal, or to a second input signal (READN), using a second resistive memory element (108) and to generate a second output signal at an output of the second synapse circuit by applying a second weight to the delayed second input signal.

Abstract: A data storage circuit includes a first memory array comprising a plurality of FeRAM memory units; a second memory array comprising a plurality of OxRAM memory units; each of the first and second memory arrays comprising: a plurality of word lines, a plurality of source lines and a plurality of bit lines; for each column each memory unit comprising: a memory cell having a first electrode and a second electrode connected to the source line associated to the memory unit; a selection transistor having a gate connected to the word line associated to the memory unit and placed in series with the memory cell between the source line and a bit line associated to of the memory unit; the data storage circuit comprising further: a data transfer stage configured to transfer data from a set of source FeRAM memory units having a common bit line to a target OxRAM unit by converting a read signal from the common bit line to a transfer voltage applied on a target line of the target OxRAM unit; the target line corresponding to

Abstract: A MEMS resonant sensor adapted to generate a pulse output signal from a signal of interest, the signal of interest being a signal having a frequency oscillating around a carrier frequency, the MEMS sensor comprising at least one processing channel for processing the signal of interest, each processing channel comprising: a demodulation unit for demodulating the signal of interest in order to form a demodulated signal, the demodulation unit comprising a frequency mixer between the signal of interest and a reference signal, the demodulated signal having a low-frequency component and a high-frequency component; a filtration unit for filtering the demodulated signal in order to form a filtered signal, the filtration unit being adapted to allow through the low-frequency component of the demodulated signal; a comparison unit for comparing the filtered signal with a fixed threshold signal in order to form a comparison signal, the comparison signal comprising rising edges and falling edges; a detection unit for detec

Abstract: This method comprises the steps: a) provide a substrate (1); b) form a layer of a first block copolymer on the substrate (1), by a technique of self-assembly such that the first layer comprises a series of first lithographic patterns extending in a first direction; c) create a first mold comprising impressions formed from the series of first lithographic patterns; d) provide a structured layer comprising a series of patterns (30), conforming to the series of first lithographic patterns, and extending in the first direction; e) form a layer (4) of a second block copolymer (40, 41) on the structured layer by a technique of self-assembly such that the second layer (4) comprises a series of second lithographic patterns (40) extending in a second direction perpendicular to the first direction; f) create a second mold comprising impressions formed from the series of second lithographic patterns (40).

Abstract: The present disclosure relates to a neural network comprising a first synapse circuit (106) configured to apply a first time delay to a first input signal (READ1) using a first resistive memory element (108) and to generate a first output signal at an output of the first synapse circuit by applying a first weight to the delayed first input signal; and a second synapse circuit (106) configured to apply a second time delay, different to the first time delay, to the first input signal, or to a second input signal (READN), using a second resistive memory element (108) and to generate a second output signal at an output of the second synapse circuit by applying a second weight to the delayed second input signal.

Abstract: A data storage circuit includes a first memory array comprising a plurality of FeRAM memory units; a second memory array comprising a plurality of OxRAM memory units; each of the first and second memory arrays comprising: a plurality of word lines, a plurality of source lines and a plurality of bit lines; for each column each memory unit comprising: a memory cell having a first electrode and a second electrode connected to the source line associated to the memory unit; a selection transistor having a gate connected to the word line associated to the memory unit and placed in series with the memory cell between the source line and a bit line associated to of the memory unit; the data storage circuit comprising further: a data transfer stage configured to transfer data from a set of source FeRAM memory units having a common bit line to a target OxRAM unit by converting a read signal from the common bit line to a transfer voltage applied on a target line of the target OxRAM unit; the target line corresponding to

Abstract: A MEMS resonant sensor adapted to generate a pulse output signal from a signal of interest, the signal of interest being a signal having a frequency oscillating around a carrier frequency, the MEMS sensor comprising at least one processing channel for processing the signal of interest, each processing channel comprising: a demodulation unit for demodulating the signal of interest in order to form a demodulated signal, the demodulation unit comprising a frequency mixer between the signal of interest and a reference signal, the demodulated signal having a low-frequency component and a high-frequency component; a filtration unit for filtering the demodulated signal in order to form a filtered signal, the filtration unit being adapted to allow through the low-frequency component of the demodulated signal; a comparison unit for comparing the filtered signal with a fixed threshold signal in order to form a comparison signal, the comparison signal comprising rising edges and falling edges; a detection unit for detec

Abstract: A processing system for processing signals from a plurality of transducers of an ultrasonic sensor in order to determine characteristic information relating to an object detected by the ultrasonic sensor is provided. The system comprises a coupling device for transforming the signals received from the transducers into pulses, and a pulse processing unit for determining the characteristic information based on the pulses delivered by the coupling device. The coupling device comprises: a thresholding unit for applying, for each signal received from a transducer, thresholding to a signal derived from the signal received from the transducer and extracting directional information contained in the phase of the derived signal; a transformation unit for transforming the derived signal into pulses containing the phase of the signal, using the information extracted by the thresholding unit.

Abstract: A method for calculating a MAC operation is performed by a memory, in particular in the neuromorphic calculation field. It allows performing the scalar product between an activation vector whose elements are binary with a vector of synaptic coefficients, quantised over M>2 levels. The calculation comprises a first phase, in which M?1 reading voltages Vread2, . . . , VreadM-1 are applied to the word lines corresponding to a positive activation and the number of passing cells in a bit line is determined for each of these voltages. In a second phase, these M?1 reading voltages are applied to the word lines corresponding to a negative activation and, for each of them, the number of passing cells in the bit line is determined again. The scalar product is then deduced from the difference between the total number of passing cells in the first phase and the total number of passing cells in the second phase.

Abstract: A memory cell, includes first and second main terminals, an auxiliary terminal; M memristor(s) between the main terminals, M?1; M primary switch(es), each in parallel with a memristor; and a secondary switch between the second main terminal and the auxiliary terminal. It is configured for writing to at least one memristor by opening each primary switch in parallel with the at least one memristor, closing each other primary switch, closing the secondary switch and applying a corresponding programming voltage between the first main terminal and the auxiliary terminal; and for reading at least one memristor by opening each primary switch in parallel with the at least one memristor, closing each other possible primary switch, opening the secondary switch and measuring a corresponding electrical quantity between the main terminals.

Abstract: The present invention concerns a method for programming a Bayesian neural network (BNN) in a RRAM memory. After the BNN has been trained on a dataset D, the joint posterior probability distribution of the synaptic coefficients, p(w|D) is decomposed into a mixture of multivariate mean-field Gaussian components by GMM. The weighting coefficients and the parameters of these multivariate Gaussian components are estimated by MDEM (Multi-Dimensional Expectation Maximization) with two constraints. According to the first constraint, the off-diagonal terms of the covariance matrix of each component are forced to zero. According to the second constraint, the couples of mean values and diagonal terms of the covariance matrix of each component are constrained to belong to a hardware compliance domain determined by a relationship between the conductance mean value and conductance standard deviation of a memristor programmed by a SET or RESET operation.

Abstract: A data storage circuit includes a matrix array of memory cells. The memory cells are configurable and non-volatile. Each one is intended to operate in either one of two operating configurations; the first operating configuration corresponding to a ferroelectric random-access memory; and the second operating configuration corresponding to a metal-oxide resistive random-access memory. Each memory cell comprises: a stack of thin layers in the following order: a first layer made of an electrically conductive material forming a lower electrode, a second layer made of a dielectric and ferroelectric material and a third layer made of electrically conductive material forming an upper electrode.

Abstract: A computer for executing a computation algorithm involving a digital variable as per at least two operating phases is provided. The computer includes a memory stage having: a first set of memories for storing a first sub-word of each digital variable; with each memory of the first set being non-volatile and having a first read endurance and a first write cyclability; a second set of memories for storing a second sub-word of each digital variable; with each memory of the second set having a second read endurance and a second write cyclability; with the first read endurance being greater than the second read endurance and the first write cyclability being less than the second write cyclability.

Abstract: A method for co-manufacturing a FeRAM and an OxRAM includes depositing a layer of first electrode carried out identically for a zone Z1 and a zone Z2; depositing a layer of hafnium dioxide-based active material carried out identically for Z1 and Z2; depositing a first conductive layer carried out identically for Z1 and Z2; making a mask at Z2, leaving Z1 free; removing the layer at Z1, with Z2 being protected by the mask; removing the mask at Z2; and depositing a second conductive layer in contact with the layer at Z2 and in contact with the layer at Z1, the material of the layer being chosen to create oxygen vacancies in the active layer and depositing a third conductive layer carried out identically for Z1 and Z2.