Abstract: A method for managing the endurance of a non-volatile rewritable memory including a dielectric material layer that switches between a high resistance state, with a first resistance value, and a low resistance state, with a second resistance value, the method including at least one of the following operations: at the end of each erasure operation: reading the first resistance value and comparing it with a first predetermined median resistance value, and determining the writing programming conditions from the comparison results; and at the end of each writing operation: reading the second resistance value and comparing it with a second predetermined median resistance value, and determining the erasure programming conditions from the comparison results, linking the programming conditions and the first and second read resistance values, the writing and erasure programming conditions being applied to the electrodes of the stack during the following writing and/or erasure operations.

Abstract: A method for programming a non-volatile resistive memory including a plurality of non-volatile resistive memory cells, each memory cell being able to switch in a reversible manner between a low resistance state in which the memory cell has an electrical resistance value lower than a first resistance threshold; and a high resistance state in which the memory cell has an electrical resistance value greater than the first resistance threshold; the programming method including determining the first resistance threshold carried out periodically during the lifetime of the resistive memory.

Abstract: A method for programming a phase change memory cell placed in an initial crystalline state, the memory cell being called of taking a plurality of resistance values belonging to a range of values called “programming window”, the method including parameterizing a lower limit of the programming window by applying to the memory cell a single gradual writing voltage pulse or a first series of identical gradual writing voltage pulses; progressively adjusting the resistance value of the memory cell by the following operations: a gradual erasing operation during which a series of identical gradual erasing voltage pulses is applied to the memory cell; a gradual writing operation during which a second series of identical gradual writing voltage pulses is applied to the memory cell; the gradual writing and gradual erasing voltage pulses have a width less than 50 ns.

Abstract: The invention relates to a non-volatile memory that comprises selection transistors. Each selection transistor includes a layer of semiconductor material with a channel region and conduction electrodes, a gate stack including a gate electrode and a gate insulator, an isolation trench between the transistors, a storage structure of the RRAM type comprising a control electrode, and a dielectric layer formed under the control electrode and in the same material as the gate insulator, comprising a central part directly above the isolation trench and ends extending directly above conduction electrodes, and configured so as to form conducting filaments. The said storage structure and the said selection transistors are formed in the same pre-metallization layer.

Abstract: A modulation device includes at least one memristive device, and a control block, the modulation device having an equivalent conductance yi(t) produced by the at least one memristive device and the control block being configured to receive a clock signal and perform a first modification of the equivalent conductance yi(t) upon receipt of each clock signal, receive an input voltage pulse and perform a second modification of the equivalent conductance yi(t) upon receipt of each input voltage pulse, the first and second modifications being in opposite directions.

Abstract: A resistive non-volatile memory cell includes a first electrode, a second electrode and an oxide layer disposed between the first electrode and the second electrode, the memory cell being capable of reversibly switching between: —a high resistance state obtained by applying a first bias voltage between the first electrode and the second electrode; and—a low resistance state obtained by applying a second bias voltage between the first electrode and the second electrode; the oxide layer including a switching zone forming a conduction path prioritised for the current passing through the memory cell when the memory cell is in the low resistance state. The oxide layer includes a first zone doped with aluminium or silicon, the aluminium or silicon being present in the first zone with an atomic concentration that is selected so as to locate the switching zone outside the first zone.

Abstract: A method for managing the endurance of a non-volatile rewritable memory including memory cells each including an ordered stack of a lower electrode, a layer of dielectric material and an upper electrode, the dielectric material switching between a high resistance state and a low resistance state, or vice versa, to enable a writing in the memory cell or an erasure of the memory cell. The method includes at the end of each writing and erasure cycle, reading the erasure conditions of the memory cell in the course of the final erasure operation of the cycle, and comparing the read erasure conditions with a predetermined median erasure value corresponding to a median resistance value which follows a predetermined dependency law linking the condition of erasure of a cycle with the condition of writing of a following cycle; and determining the writing conditions from the results of the comparison.

Abstract: A system including: a memory including a plurality of pages; and a control circuit suitable for delivering user access to the memory and for implementing a balancing method for the wear of the memory, including movement of data within the memory, in which the control circuit is suitable for delivering, between the first and second consecutive page read or write operations of the wear balancing method and between the second and a third consecutive page read or write operation of the wear balancing method, one or more user accesses to the pages of the memory.

Abstract: A method for managing the endurance of a non-volatile rewritable memory including memory cells each including an ordered stack of a lower electrode, a layer of dielectric material and an upper electrode, the dielectric material switching between a high resistance state and a low resistance state, or vice versa, to enable a writing in the memory cell or an erasure of the memory cell. The method includes at the end of each writing and erasure cycle, reading the erasure conditions of the memory cell in the course of the final erasure operation of the cycle, and comparing the read erasure conditions with a predetermined median erasure value corresponding to a median resistance value which follows a predetermined dependency law linking the condition of erasure of a cycle with the condition of writing of a following cycle; and determining the writing conditions from the results of the comparison.

Abstract: The invention relates to a non-volatile memory that comprises selection transistors. Each selection transistor includes a layer of semiconductor material with a channel region and conduction electrodes, a gate stack including a gate electrode and a gate insulator, an isolation trench between the transistors, a storage structure of the RRAM type comprising a control electrode, and a dielectric layer formed under the control electrode and in the same material as the gate insulator, comprising a central part directly above the isolation trench and ends extending directly above conduction electrodes, and configured so as to form conducting filaments. The said storage structure and the said selection transistors are formed in the same pre-metallization layer.

Abstract: A method for managing the endurance of a non-volatile rewritable memory including a dielectric material layer that switches between a high resistance state, with a first resistance value, and a low resistance state, with a second resistance value, the method including at least one of the following operations: at the end of each erasure operation: reading the first resistance value and comparing it with a first predetermined median resistance value, and determining the writing programming conditions from the comparison results; and at the end of each writing operation: reading the second resistance value and comparing it with a second predetermined median resistance value, and determining the erasure programming conditions from the comparison results, linking the programming conditions and the first and second read resistance values, the writing and erasure programming conditions being applied to the electrodes of the stack during the following writing and/or erasure operations.

Abstract: Method for producing a device with transistors distributed over several levels and provided with a resistive memory cell having an electrode formed of a conductor portion belonging to a connection element connected to a transistor of a given level.

Abstract: The invention more particularly relates to a resistive memory cell comprising a first and a second metal electrodes and a solid electrolyte positioned between the first and the second metal electrodes, with the solid electrolyte comprising a commutation layer in contact with the first electrode and a dielectric layer, with said resistive memory cell being able to be electrically modified so as to switch from a first resistive state to a second resistive state (state LRS) wherein the resistance (RON) of the memory cell is at least ten times smaller than the resistance (ROFF) of the memory cell in the HRS state, in the LRS state the first electrode being so arranged as to supply metal ions intended to form at least a conductive filament through said commutation layer, with the cell being characterized in that, in the LRS state, the memory cell is conductive for a range of voltages between 0 Volts and VREST 2 .

Abstract: A resistive random access memory device includes a first electrode; a solid electrolyte made of metal oxide extending onto the first electrode; a second electrode able to supply mobile ions circulating in the solid electrolyte made of metal oxide to the first electrode to form a conductive filament between the first and second electrodes when a voltage is applied between the first and second electrodes; an interface layer including a transition metal from groups 3, 4, 5 or 6 of the periodic table and a chalcogen element; the interface layer extending onto the solid electrolyte made of metal oxide, the second electrode extending onto the interface layer.

Abstract: A method for unsupervised sorting, in real time, of action potentials of biological neurons by a network of artificial neurons including input, intermediate and output layers, the method according to which: the input layer receives an electrical signal measuring an electrical activity of biological neurons, the electrical signal having a variable amplitude as a function of action potentials emitted by the plurality of biological neurons over time; the input layer converts the amplitude of the electrical signal into a train of first spikes; the input layer transmits the train of first spikes to the intermediate layer; the intermediate layer converts the train of first spikes into a train of second spikes; the intermediate layer transmits the train of second spikes to the output layer; as a function of the train of second spikes, the output layer sorts each occurrence of each type of action potential present in the electrical signal.

Abstract: A resistive random access memory device includes a first electrode made of inert material; a second electrode made of soluble material; a solid electrolyte including a region made of an oxide of a first metal element, referred to as first metal oxide doped by a second element, distinct from the first metal and able to form a second oxide, the second element being selected such that the band gap energy of the second oxide is strictly greater than the band gap energy of the first metal oxide, the atomic percentage of the second element within the region of the solid electrolyte being comprised between 5% and 20%.

Abstract: Method for producing a device with transistors distributed over several levels and provided with a resistive memory cell having an electrode formed of a conductor portion belonging to a connection element connected to a transistor of a given level.

Abstract: A programming method for an artificial neuron network having synapses, each including a single resistive random-access memory having first and second electrodes on either side of an active zone, the method including determining a number N of conductance intervals, where N?3; for each memory: choosing a conductance interval from amongst the N intervals; a step i) for application of a voltage pulse of a first type between the first and second electrodes, and for reading the conductance value of the memory; if the conductance value does not belong to the previously chosen conductance interval, a sub-step ii) for application of a voltage pulse of a second type between the first and second electrodes, and for reading the conductance value; if the conductance value does not belong to the chosen conductance interval, a step according to which step i) is reiterated, with steps i) and ii) being repeated until the conductance value belongs to the interval.

Abstract: A system including: a first memory including several portions each of several pages, this memory including first and second ports that enable simultaneous access to two pages of distinct portions of the memory; and a control circuit suitable for implementing, via the second port, a method for balancing the wear of the memory, including movements of data within the memory, while authorizing simultaneous user access to the memory contents via the first port.

Abstract: A system including: a memory including a plurality of pages; and a control circuit suitable for delivering user access to the memory and for implementing a balancing method for the wear of the memory, including movement of data within the memory, in which the control circuit is suitable for delivering, between the first and second consecutive page read or write operations of the wear balancing method and between the second and a third consecutive page read or write operation of the wear balancing method, one or more user accesses to the pages of the memory.