Patents by Inventor Elisa Vianello
Elisa Vianello has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11217307Abstract: The present disclosure relates to a method of programming resistive memory cells of a resistive memory, the method comprising: applying, by a programming circuit based on a first target resistive state, an initial resistance modification to a first cell of the resistive memory to change its resistance from an initial resistive state to a first new resistance; comparing, by the programming circuit, the first new resistance of the first cell with a resistance range of the first target resistive state and with a target resistance range associated with the first target resistive state; and if it is determined that the first new resistance is outside the resistance range of the target resistive state and inside the target resistance range, applying by the programming circuit one or more further resistance modifications to the first cell to increase or decrease its resistance.Type: GrantFiled: April 5, 2019Date of Patent: January 4, 2022Assignees: Commissariat à l'Energie Atomique et aux Energies Alternatives, The Board of Trustees of the Leland Stanford Junior UniversityInventors: Elisa Vianello, Etienne Nowak, Binh Quang Le, Subhasish Mitra, Fan Tony Wu, Philip Wong
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Patent number: 11189792Abstract: A resistive non-volatile memory cell includes a first electrode, a second electrode and an oxide layer disposed between the first electrode and the second electrode, the memory cell being capable of reversibly switching between: —a high resistance state obtained by applying a first bias voltage between the first electrode and the second electrode; and—a low resistance state obtained by applying a second bias voltage between the first electrode and the second electrode; the oxide layer including a switching zone forming a conduction path prioritised for the current passing through the memory cell when the memory cell is in the low resistance state. The oxide layer includes a first zone doped with aluminium or silicon, the aluminium or silicon being present in the first zone with an atomic concentration that is selected so as to locate the switching zone outside the first zone.Type: GrantFiled: September 8, 2017Date of Patent: November 30, 2021Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Laurent Grenouillet, Marios Barlas, Philippe Blaise, Benoît Sklenard, Elisa Vianello
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Publication number: 20210367149Abstract: This method comprises the steps: a) provide a substrate (1); b) form a layer of a first block copolymer on the substrate (1), by a technique of self-assembly such that the first layer comprises a series of first lithographic patterns extending in a first direction; c) create a first mold comprising impressions formed from the series of first lithographic patterns; d) provide a structured layer comprising a series of patterns (30), conforming to the series of first lithographic patterns, and extending in the first direction; e) form a layer (4) of a second block copolymer (40, 41) on the structured layer by a technique of self-assembly such that the second layer (4) comprises a series of second lithographic patterns (40) extending in a second direction perpendicular to the first direction; f) create a second mold comprising impressions formed from the series of second lithographic patterns (40).Type: ApplicationFiled: May 19, 2021Publication date: November 25, 2021Applicant: Commissariat à l'Energie Atomique et aux Energies AlternativesInventors: Raluca TIRON, Gaëlle CHAMIOT-MAITRAL, Elisa VIANELLO
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Publication number: 20210350218Abstract: A Bayesian neural network including an input layer, and, an output layer, and, possibly, one or more hidden layer(s). Each neuron of a layer is connected at its input with a plurality of synapses, the synapses of the plurality being implemented as a RRAM array constituted of cells, each column of the array being associated with a synapse and each row of the array being associated with an instance of the set of synaptic coefficients, the cells of a row of the RRAM being programmed during a SET operation with respective programming current intensities, the programming intensity of a cell being derived from the median value of a Gaussian component obtained by GMM decomposition into Gaussian components of the marginal posterior probability of the corresponding synaptic coefficient, once the BNN model has been trained on a training dataset.Type: ApplicationFiled: April 7, 2021Publication date: November 11, 2021Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Thomas DALGATY, Niccolo CASTELLANI, Elisa VIANELLO
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Patent number: 11145812Abstract: A resistive random access memory device includes a first electrode; a solid electrolyte made of metal oxide extending onto the first electrode; a second electrode able to supply mobile ions circulating in the solid electrolyte made of metal oxide to the first electrode to form a conductive filament between the first and second electrodes when a voltage is applied between the first and second electrodes; an interface layer including a transition metal from groups 3, 4, 5 or 6 of the periodic table and a chalcogen element; the interface layer extending onto the solid electrolyte made of metal oxide, the second electrode extending onto the interface layer.Type: GrantFiled: October 16, 2017Date of Patent: October 12, 2021Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Gabriel Molas, Philippe Blaise, Faiz Dahmani, Elisa Vianello
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Publication number: 20210232905Abstract: The present disclosure relates to a routing circuit for routing signals between neuron circuits of an artificial neural network, the routing circuit comprising: a first memory cell (302) having an input coupled to a first input line (304) of the routing circuit and an output coupled to a first column line (308); a second memory cell (302) having an input coupled to a second input line (304) of the routing circuit and an output coupled to the first column line (308); and a first comparator circuit (310) configured to compare a signal (IREAD1) on the first column line (308) with a reference level, and to selectively assert a signal (VOUT1) on a first output line (312) of the routing circuit based on the comparison.Type: ApplicationFiled: January 22, 2021Publication date: July 29, 2021Inventors: Thomas DALGATY, Giacomo INDIVERI, Melika PAYVAND, Elisas VIANELLO
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Patent number: 11017293Abstract: A programming method for an artificial neuron network having synapses, each including a single resistive random-access memory having first and second electrodes on either side of an active zone, the method including determining a number N of conductance intervals, where N?3; for each memory: choosing a conductance interval from amongst the N intervals; a step i) for application of a voltage pulse of a first type between the first and second electrodes, and for reading the conductance value of the memory; if the conductance value does not belong to the previously chosen conductance interval, a sub-step ii) for application of a voltage pulse of a second type between the first and second electrodes, and for reading the conductance value; if the conductance value does not belong to the chosen conductance interval, a step according to which step i) is reiterated, with steps i) and ii) being repeated until the conductance value belongs to the interval.Type: GrantFiled: August 15, 2016Date of Patent: May 25, 2021Assignee: COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVESInventors: Elisa Vianello, Olivier Bichler
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Publication number: 20210150409Abstract: A method for training a logistic regression classifier on a dataset by using a resistive RAM as hardware accelerator, each row of the resistive RAM including cells which can be programmed in a first resistance state or a second resistance state. The probability of a data element belonging to a class is modelled by a logistic function applied to a score of the element, where is a parameter vector of the model. The logistic regression classifier is trained by populating the resistive RAM with samples of a model parameter vector which are obtained by MCMC sampling. Once populated, the resistive RAM can be used for classifying new data.Type: ApplicationFiled: November 17, 2020Publication date: May 20, 2021Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Thomas DALGATY, Elisa VIANELLO
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Patent number: 10985317Abstract: A device for selecting a storage cell, includes a first electrode, a second electrode and an oxide layer disposed between the first electrode and the second electrode, wherein the oxide layer is doped with a first element from column IV of the periodic table.Type: GrantFiled: September 8, 2017Date of Patent: April 20, 2021Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Marios Barlas, Philippe Blaise, Laurent Grenouillet, Benoît Sklenard, Elisa Vianello
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Publication number: 20210035638Abstract: The present disclosure relates to a method of programming resistive memory cells of a resistive memory, the method comprising: applying, by a programming circuit based on a first target resistive state, an initial resistance modification to a first cell of the resistive memory to change its resistance from an initial resistive state to a first new resistance; comparing, by the programming circuit, the first new resistance of the first cell with a resistance range of the first target resistive state and with a target resistance range associated with the first target resistive state; and if it is determined that the first new resistance is outside the resistance range of the target resistive state and inside the target resistance range, applying by the programming circuit one or more further resistance modifications to the first cell to increase or decrease its resistance.Type: ApplicationFiled: April 5, 2019Publication date: February 4, 2021Inventors: Elisa VIANELLO, Etienne NOWAK, Binh Quang LE, Subhasish MITRA, Fan Tony WU, Philip WONG
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Patent number: 10861545Abstract: A programmable artificial neuron emitting an output signal controlled by at least one control parameter, includes, for each control parameter, a capacitor and at least one block including at least one multiplexer configured to be in two states: a programming state and an operating state; a transistor; and a non-volatile resistive random access memory connected in series with the transistor, the capacitor and the resistive random access memory being mounted in parallel. The multiplexer is configured to, when it is in the programming state, set a resistance value of the resistive random access memory to set the value of the control parameter; when it is in the operating state, conserve the set resistance value of the resistive random access memory.Type: GrantFiled: July 31, 2019Date of Patent: December 8, 2020Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Thomas Dalgaty, Elisa Vianello
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Patent number: 10839902Abstract: A method for programming a non-volatile resistive memory including a plurality of non-volatile resistive memory cells, each memory cell being able to switch in a reversible manner between a low resistance state in which the memory cell has an electrical resistance value lower than a first resistance threshold; and a high resistance state in which the memory cell has an electrical resistance value greater than the first resistance threshold; the programming method including determining the first resistance threshold carried out periodically during the lifetime of the resistive memory.Type: GrantFiled: April 26, 2019Date of Patent: November 17, 2020Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Alessandro Grossi, Elisa Vianello
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Publication number: 20200321397Abstract: A method of producing a recurrent neural network computer includes consecutive steps of providing a substrate with a first electrode; structuring the first electrode by etching using a first mask made of block copolymers, such that said electrode has free regions which are randomly spatially distributed; forming a resistive-RAM-type memory layer on the first structured electrode; forming a second electrode on the memory layer; and structuring the second electrode by etching, using a second mask made of block copolymers such that said electrode has free regions which are randomly spatially distributed.Type: ApplicationFiled: September 25, 2018Publication date: October 8, 2020Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Elisa VIANELLO, Catherine CARABASSE, Selina LA BARBERA, Raluca TIRON
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Patent number: 10755754Abstract: A method for programming a phase change memory cell placed in an initial crystalline state, the memory cell being called of taking a plurality of resistance values belonging to a range of values called “programming window”, the method including parameterizing a lower limit of the programming window by applying to the memory cell a single gradual writing voltage pulse or a first series of identical gradual writing voltage pulses; progressively adjusting the resistance value of the memory cell by the following operations: a gradual erasing operation during which a series of identical gradual erasing voltage pulses is applied to the memory cell; a gradual writing operation during which a second series of identical gradual writing voltage pulses is applied to the memory cell; the gradual writing and gradual erasing voltage pulses have a width less than 50 ns.Type: GrantFiled: March 8, 2019Date of Patent: August 25, 2020Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Selina La Barbera, Niccolo Castellani, Gabriele Navarro, Elisa Vianello
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Patent number: 10741757Abstract: The disclosed process includes the successive stages of providing a substrate comprising a dielectric layer; forming a first layer of block copolymers on a part of the dielectric layer, so that the dielectric layer exhibits free zones with a random spatial distribution; etching the free zones, so as to structure the dielectric layer; removing the first layer of block copolymers; forming a first electrode on the structured dielectric layer; forming a memory layer, of resistive memory type, on the first electrode; forming a second electrode on the memory layer; forming a second layer of block copolymers on a part of the second electrode, so that the second electrode exhibits free zones with a random spatial distribution; etching the free zones, so as to structure the second electrode; and removing the second layer of block copolymers.Type: GrantFiled: June 4, 2019Date of Patent: August 11, 2020Assignee: Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Elisa Vianello, Selina La Barbera, Jean-Francois Nodin, Raluca Tiron
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Publication number: 20200127199Abstract: A device for selecting a storage cell, includes a first electrode, a second electrode and an oxide layer disposed between the first electrode and the second electrode, wherein the oxide layer is doped with a first element from column IV of the periodic table.Type: ApplicationFiled: September 8, 2017Publication date: April 23, 2020Inventors: Mario BARLAS, Philippe BLAISE, Laurent GRENOUILLET, Benoît SKLENARD, Elisa VIANELLO
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Patent number: 10559355Abstract: The invention relates to a resistive memory (5) including resistive elements, the resistance of each resistive element being capable of alternating between a high value in a first range of values and a low value in a second range of values smaller than the high value, the memory further comprising a device (14) for switching the resistance of at least one resistive element selected from among the resistive elements between the high and low values, the device including a first circuit capable of applying an increasing voltage across the selected resistive element while the selected resistive element is at the high value or at the low value, a second circuit capable of detecting the switching of the resistance of the selected resistive element, and a third circuit capable of interrupting the current flowing through the selected resistive element on detection of the switching.Type: GrantFiled: September 8, 2015Date of Patent: February 11, 2020Assignee: Commissariat a l'energie atomique et aux energies alternativesInventors: Michel Harrand, Elisa Vianello, Olivier Thomas, Bastien Giraud
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Publication number: 20200043552Abstract: A programmable artificial neuron emitting an output signal controlled by at least one control parameter, includes, for each control parameter, a capacitor and at least one block including at least one multiplexer configured to be in two states: a programming state and an operating state; a transistor; and a non-volatile resistive random access memory connected in series with the transistor, the capacitor and the resistive random access memory being mounted in parallel. The multiplexer is configured to, when it is in the programming state, set a resistance value of the resistive random access memory to set the value of the control parameter; when it is in the operating state, conserve the set resistance value of the resistive random access memory.Type: ApplicationFiled: July 31, 2019Publication date: February 6, 2020Inventors: Thomas DALGATY, Elisa VIANELLO
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Patent number: 10540099Abstract: A system including: a first memory including several portions each of several pages, this memory including first and second ports that enable simultaneous access to two pages of distinct portions of the memory; and a control circuit suitable for implementing, via the second port, a method for balancing the wear of the memory, including movements of data within the memory, while authorizing simultaneous user access to the memory contents via the first port.Type: GrantFiled: December 12, 2014Date of Patent: January 21, 2020Assignee: Commissariat à l'Énergie Atomique et aux Énergies AlternativesInventors: Michel Harrand, Elisa Vianello
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Publication number: 20190393412Abstract: The disclosed process includes the successive stages of providing a substrate comprising a dielectric layer; forming a first layer of block copolymers on a part of the dielectric layer, so that the dielectric layer exhibits free zones with a random spatial distribution; etching the free zones, so as to structure the dielectric layer; removing the first layer of block copolymers; forming a first electrode on the structured dielectric layer; forming a memory layer, of resistive memory type, on the first electrode; forming a second electrode on the memory layer; forming a second layer of block copolymers on a part of the second electrode, so that the second electrode exhibits free zones with a random spatial distribution; etching the free zones, so as to structure the second electrode; and removing the second layer of block copolymers.Type: ApplicationFiled: June 4, 2019Publication date: December 26, 2019Applicant: Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Elisa VIANELLO, Selina La Barbera, Jean-Francois Nodin, Raluca Tiron