Abstract: A circuit arrangement includes a signal processing unit and a regulation unit. The signal processing unit processes an input signal to form an analog output signal. The regulation unit is coupled to the signal processing unit in order to produce a digital regulation signal as a function of the analog output signal for regulation of the analog output signal.

Abstract: An apparatus provides a baseband signal for exploiting receive antenna diversity by means of a digital baseband processor. The apparatus includes a combiner configured to temporally alternately select at least one sample of a first received signal corresponding to a first receive antenna and at least one sample of a second received signal corresponding to a second receive antenna and to interleave the selected samples of the first and second received signal to obtain a temporally continuous stream of samples of a baseband representation of a combined signal at an output of the combiner as the baseband signal for exploiting receive antenna diversity.

Abstract: An apparatus provides a baseband signal for exploiting receive antenna diversity by means of a digital baseband processor. The apparatus includes a combiner configured to temporally delay a first received signal corresponding to a first receive antenna with respect to a second received signal corresponding to a second receive antenna, and to add the delayed first received signal and the second received signal to obtain a baseband representation of a combined signal at an output of the combiner as the baseband signal for exploiting receive antenna diversity.

Abstract: Some embodiments disclosed herein relate to a transmitter. The transmitter includes a digital modulator adapted to provide a digital modulated RF signal based on a multi-bit representation of data and a multi-bit representation of a carrier wave. A digital-to-analog converter (DAC) is adapted to generate an analog modulated RF signal based on the digital modulated RF signal. A resonant circuit coupled to an output of the DAC and adapted to filter undesired frequency components from the analog modulated RF signal.

Abstract: An amplifier assembly and also a receiver including such an amplifier assembly is disclosed, wherein the amplifier includes a programming input for setting the gain thereof. The signal level at the output of the amplifier is compared with a reference level and a counter is incremented in a step-by-step fashion such that the gain in the amplifier is reduced for as long as the output level lies above the reference level. The amplifier assembly enables frequency-dependent received field strength fluctuations that occur in frequency hopping methods to be corrected in a manner dependent on the conditions in the current time slot. The assembly is also suitable for modulation methods that use a modulation with phase and amplitude variation.

Abstract: An amplifier assembly and also a receiver including such an amplifier assembly is disclosed, wherein the amplifier includes a programming input for setting the gain thereof. The signal level at the output of the amplifier is compared with a reference level and a counter is incremented in a step-by-step fashion such that the gain in the amplifier is reduced for as long as the output level lies above the reference level. The amplifier assembly enables frequency-dependent received field strength fluctuations that occur in frequency hopping methods to be corrected in a manner dependent on the conditions in the current time slot. The assembly is also suitable for modulation methods that use a modulation with phase and amplitude variation.

Abstract: The digital filter has a finite impulse response, whose length corresponds at most to the duration of N input values, with the filter emitting an output signal which is n-times oversampled in comparison to the input signal (I, Q). In this case, a device (38.1-38.5) for storage of a plurality of N look-up tables is provided in the filter. n data values are stored per value in each look-up table for a plurality of k possible values of the input signal. Each data value is in this case characteristic of the product of a coefficient of the impulse response and a value of the input signal (I, Q).

Abstract: A transmitting and receiving arrangement as well as a method for transmission of monitoring and/or payload data in a transmitting and receiving arrangement for a wirefree communications system has a device which processes baseband for processing digital signals to form a baseband signal and a device which processes radio frequency for conversion of the baseband signal to a radio frequency signal. Monitoring and/or payload data are/is transmitted in the form of data packets via at least one channel of a channel-oriented link between the device which processes baseband and the device which processes radio frequency.

Abstract: An amplifier assembly and also a receiver including such an amplifier assembly is disclosed, wherein the amplifier includes a programming input for setting the gain thereof. The signal level at the output of the amplifier is compared with a reference level and a counter is incremented in a step-by-step fashion such that the gain in the amplifier is reduced for as long as the output level lies above the reference level. The amplifier assembly enables frequency-dependent received field strength fluctuations that occur in frequency hopping methods to be corrected in a manner dependent on the conditions in the current time slot. The assembly is also suitable for modulation methods that use a modulation with phase and amplitude variation.

Abstract: A transmitting and receiving arrangement as well as a method for transmission of monitoring and/or payload data in a transmitting and receiving arrangement for a wirefree communications system has a device which processes baseband for processing digital signals to form a baseband signal and a device which processes radio frequency for conversion of the baseband signal to a radio frequency signal. Monitoring and/or payload data are/is transmitted in the form of data packets via at least one channel of a channel-oriented link between the device which processes baseband and the device which processes radio frequency.

Abstract: The present invention relates to receiver equipment with AC-coupled receiver circuits and AC coupling filters. A switch connected between a first stage and a second stage among the receiver circuits is adapted to switch from a high coupling corner frequency, for rapid settling of a signal during preparation of data reception, to a low corner frequency, for low signal distortion during data reception. The receiver circuits are adapted to use known properties in the signal to perform the switch at a time when the short term DC-components of the signal are as low as possible.

Abstract: The invention relates to a phase comparison circuit including a reference input and a feedback input, and an output provided with a controlled oscillator which is connected thereto. A frequency divider with an adjustable division ratio resides in the feedback path of the phase-lock loop. The phase-lock loop includes a frequency adjusting arrangement having a first and a second control input, a first output which is connected to the frequency divider and is used to generate a digital regulating signal, and a second output which is coupled to the controlled oscillator and is used to generate an analog control signal. The first control input is embodied in such a way as to adjust a frequency of the phase-lock loop, and the second control input is embodied in such a way as to switch the frequency of the phase-lock loop according to a frequency offset. The phase-lock loop can advantageously be used to compensate frequency offsets of received signals.

Abstract: In an embodiment, a radio transmitter may be provided. The radio transmitter may include a radio transmitter control loop; and a controller configured in such a way that it operates the radio transmitter control loop as a closed control loop in a first operating mode, and that it operates the radio transmitter control loop as an open control loop in a second operating mode.

Abstract: An arrangement for testing a plurality of capacitances in a capacitance array of an integrated circuit includes a power supply and a means for cyclically charging and discharging at least one of the capacitances. In this arrangement, the cycle frequency is dependent on the value of the capacitance. The cycle frequency or a quantity characteristic associated therewith is measured by a means to ascertain a value of the capacitance under test.

Abstract: A measuring circuit for the output of a power amplifier and a power amplifier comprising the measuring circuit comprises a first transistor (4f). The output current (27) of the first transistor (4f) is characteristic of the output current (28) of the amplifier (20), in particular, the above is essentially proportional to the output current (28) of the amplifier (20). The first transistor (4f) is controlled in parallel to at least one second transistor (4a-4e), driving the amplifier output (8).

Abstract: A circuit arrangement includes a signal processing unit and a regulation unit. The signal processing unit processes an input signal to form an analog output signal. The regulation unit is coupled to the signal processing unit in order to produce a digital regulation signal as a function of the analog output signal for regulation of the analog output signal.

Abstract: A radio receiver with a low intermediate frequency has a first mixer stage that can be fed with a modulated input signal and at whose output a complex intermediate frequency signal can be derived. Connected downstream of the first mixer stage is a limiting amplifier at whose output the intermediate frequency signal is present in a discrete-value and continuous-time fashion. A sampling device, for sampling the intermediate frequency signal, and a digital demodulator unit are connected to the output of this limiter. The demodulated input signal can be derived at the output of this digital demodulator unit. The present radio receiver requires a low chip area in conjunction with low power consumption, but offers a high sensitivity and accuracy based on the digitally implemented demodulation.

Abstract: The invention provides a phase locked loop having a modulator which is based on a ?? fractional N phase locked loop. In the forward path of the PLL, the output of the oscillator has an additional frequency divider which provides the output frequency of the PLL in a plurality of different phases. A multiplexer which is connected upstream of the multimodulus divider in the PLL's feedback path and which is actuated by the ?? modulator, like the divider, selects the respective desired phase. This allows the minimum step size of the division factors to be reduced to values of less than 1 relative to the output frequency, which significantly reduces the quantization noise. The PLL bandwidth may therefore advantageously be the same size as the modulation bandwidth.

Abstract: The invention is directed to a phase locked loop with a ?? modulator. A multimodulus divider in the feedback path of the PLL is actuated by the ?? modulator. The latter has a design which can be described by a complex transfer function H(s) in the Laplace plane, said transfer function having a complex-conjugate pair of pole points. The arrangement allows a significant reduction in the noise in critical frequency domains and hence allows adherence to transmission masks based on radio specification even when the PLL bandwidth is as large as the modulation bandwidth.

Abstract: A measuring circuit for the output of a power amplifier and a power amplifier comprising the measuring circuit comprises a first transistor (4f). The output current (27) of the first transistor (4f) is characteristic of the output current (28) of the amplifier (20), in particular, the above is essentially proportional to the output current (28) of the amplifier (20). The first transistor (4f) is controlled in parallel to at least one second transistor (4a-4e), driving the amplifier output (8).