Abstract: The present invention relates to receiver equipment with AC-coupled receiver circuits and AC coupling filters. A switch connected between a first stage and a second stage among the receiver circuits is adapted to switch from a high coupling corner frequency, for rapid settling of a signal during preparation of data reception, to a low corner frequency, for low signal distortion during data reception. The receiver circuits are adapted to use known properties in the signal to perform the switch at a time when the short term DC-components of the signal are as low as possible.

Abstract: The invention relates to a phase comparison circuit including a reference input and a feedback input, and an output provided with a controlled oscillator which is connected thereto. A frequency divider with an adjustable division ratio resides in the feedback path of the phase-lock loop. The phase-lock loop includes a frequency adjusting arrangement having a first and a second control input, a first output which is connected to the frequency divider and is used to generate a digital regulating signal, and a second output which is coupled to the controlled oscillator and is used to generate an analog control signal. The first control input is embodied in such a way as to adjust a frequency of the phase-lock loop, and the second control input is embodied in such a way as to switch the frequency of the phase-lock loop according to a frequency offset. The phase-lock loop can advantageously be used to compensate frequency offsets of received signals.

Abstract: A transmitting and receiving arrangement as well as a method for transmission of monitoring and/or payload data in a transmitting and receiving arrangement for a wirefree communications system has a device which processes baseband for processing digital signals to form a baseband signal and a device which processes radio frequency for conversion of the baseband signal to a radio frequency signal. Monitoring and/or payload data are/is transmitted in the form of data packets via at least one channel of a channel-oriented link between the device which processes baseband and the device which processes radio frequency.

Abstract: In a receiver circuit for demodulating a high-frequency signal, a limiting amplifier stage with a downstream sigma-delta converter is connected in series with a mixer stage that transforms a high-frequency signal that is supplied at its input into an intermediate-frequency signal. The intermediate-frequency signal at the output of the limiting amplifier stage is value-discrete and time-continuous. The described receiver architecture has a high sensitivity, is substantially independent of production tolerances, and occupies a small area; therefore, it is particularly suitable for mobile radio applications.

Abstract: The invention is directed to a phase locked loop with a ?? modulator. A multimodulus divider in the feedback path of the PLL is actuated by the ?? modulator. The latter has a design which can be described by a complex transfer function H(s) in the Laplace plane, said transfer function having a complex-conjugate pair of pole points. The arrangement allows a significant reduction in the noise in critical frequency domains and hence allows adherence to transmission masks based on radio specification even when the PLL bandwidth is as large as the modulation bandwidth.

Abstract: The invention is directed to a phase locked loop with a ?? modulator. A multimodulus divider in the feedback path of the PLL is actuated by the ?? modulator. The latter has a design which can be described by a complex transfer function H(s) in the Laplace plane, said transfer function having a complex-conjugate pair of pole points. The arrangement allows a significant reduction in the noise in critical frequency domains and hence allows adherence to transmission masks based on radio specification even when the PLL bandwidth is as large as the modulation bandwidth.

Abstract: The digital filter has a finite impulse response, whose length corresponds at most to the duration of N input values, with the filter emitting an output signal which is n-times oversampled in comparison to the input signal (I, Q). In this case, a means (38.1-38.5) for storage of a plurality of N look-up tables is provided in the filter. n data values are stored per value in each look-up table for a plurality of k possible values of the input signal. Each data value is in this case characteristic of the product of a coefficient of the impulse response and a value of the input signal (I, Q).

Abstract: A multiplier circuit has an analog multiplier with two signal inputs. A respective switching device is connected to each one of the two signal inputs of the analog multiplier for periodically reversing the polarity of the input voltages. A clock signal that can be fed to the switching devices has a changeover frequency that is preferably greater than or equal to twice the useful signal frequency. This suppresses offset-governed crosstalk of the input signals to the output of the analog multiplier. This principle can also be employed in quadricorrelators.

Abstract: The invention is directed to a phase locked loop with a ?? modulator. A multimodulus divider in the feedback path of the PLL is actuated by the ?? modulator. The latter has a design which can be described by a complex transfer function H(s) in the Laplace plane, said transfer function having a complex-conjugate pair of pole points. The arrangement allows a significant reduction in the noise in critical frequency domains and hence allows adherence to transmission masks based on radio specification even when the PLL bandwidth is as large as the modulation bandwidth.

Abstract: A demodulator has a resistor and a capacitor that may be subject to tolerances. For tolerance correction, the FM demodulator is preferably supplied with a reference frequency, which corresponds to the nominal mid-frequency of the demodulator, which is a function of the resistor and the capacitor. Any discrepancy between the actual mid-frequency of the demodulator and its nominal mid-frequency leads to the production of a voltage that differs from a nominal voltage at the output. A detector detects this error and adjusts the values of the resistor or capacitor until the error between the nominal voltage and the voltage is zero or is a minimum. The described principle can be used, for example, in integrated mobile radio receivers.

Abstract: The invention provides a phase locked loop having a modulator which is based on a ?? fractional N phase locked loop. In the forward path of the PLL, the output of the oscillator has an additional frequency divider which provides the output frequency of the PLL in a plurality of different phases. A multiplexer which is connected upstream of the multimodulus divider in the PLL's feedback path and which is actuated by the ?? modulator, like the divider, selects the respective desired phase. This allows the minimum step size of the division factors to be reduced to values of less than 1 relative to the output frequency, which significantly reduces the quantization noise. The PLL bandwidth may therefore advantageously be the same size as the modulation bandwidth.

Abstract: A receiving arrangement for a cordless communication system includes an analog radio-frequency input section and a digital signal processing device connected downstream thereof. The digital signal processing device has an analog/digital converter which is followed by a digital mixing stage and a decimation unit. The decimation factor of the decimation unit is switchable in order to achieve an advantageous implementation for various systems.

Abstract: An amplifier assembly and also a receiver including such an amplifier assembly is disclosed, wherein the amplifier includes a programming input for setting the gain thereof. The signal level at the output of the amplifier is compared with a reference level and a counter is incremented in a step-by-step fashion such that the gain in the amplifier is reduced for as long as the output level lies above the reference level. The amplifier assembly enables frequency-dependent received field strength fluctuations that occur in frequency hopping methods to be corrected in a manner dependent on the conditions in the current time slot. The assembly is also suitable for modulation methods that use a modulation with phase and amplitude variation.

Abstract: An arrangement for testing a plurality of capacitances in a capacitance array of an integrated circuit includes a power supply and a means for cyclically charging and discharging at least one of the capacitances. In this arrangement, the cycle frequency is dependent on the value of the capacitance. The cycle frequency or a quantity characteristic associated therewith is measured by a means to ascertain a value of the capacitance under test.

Abstract: To demodulate a frequency-modulated signal having an offset, two time constants are provided in a filter unit. The filter unit has two analog or digital low-pass filters or high-pass filters. A first switch is used to change over between the two time constants. If a plurality of bits having the same state succeed one another in a setting mode, the first switch is used to change over to a slower time constant so as not to corrupt the threshold voltage that is to be ascertained. In a normal mode, the stored threshold voltage is, then, used to distinguish between the states coded in an input signal. In such a context, the slower time constant is valid in the normal mode.

Abstract: A demodulator has a resistor and a capacitor that may be subject to tolerances. For tolerance correction, the FM demodulator is preferably supplied with a reference frequency, which corresponds to the nominal mid-frequency of the demodulator, which is a function of the resistor and the capacitor. Any discrepancy between the actual mid-frequency of the demodulator and its nominal mid-frequency leads to the production of a voltage that differs from a nominal voltage at the output. A detector detects this error and adjusts the values of the resistor or capacitor until the error between the nominal voltage and the voltage is zero or is a minimum. The described principle can be used, for example, in integrated mobile radio receivers.

Abstract: In a receiver circuit for demodulating a high-frequency signal, a limiting amplifier stage with a downstream sigma-delta converter is connected in series with a mixer stage that transforms a high-frequency signal that is supplied at its input into an intermediate-frequency signal. The intermediate-frequency signal at the output of the limiting amplifier stage is value-discrete and time-continuous. The described receiver architecture has a high sensitivity, is substantially independent of production tolerances, and occupies a small area; therefore, it is particularly suitable for mobile radio applications.

Abstract: A radio receiver with a low intermediate frequency has a first mixer stage that can be fed with a modulated input signal and at whose output a complex intermediate frequency signal can be derived. Connected downstream of the first mixer stage is a limiting amplifier at whose output the intermediate frequency signal is present in a discrete-value and continuous-time fashion. A sampling device, for sampling the intermediate frequency signal, and a digital demodulator unit are connected to the output of this limiter. The demodulated input signal can be derived at the output of this digital demodulator unit. The present radio receiver requires a low chip area in conjunction with low power consumption, but offers a high sensitivity and accuracy based on the digitally implemented demodulation.

Abstract: To demodulate an amplitude-modulated signal having an offset, two time constants are provided in a filter unit. The filter unit has two analog or digital low-pass filters or high-pass filters. A first switch is used to change over between the two time constants. If a plurality of bits having the same state succeed one another in a setting mode, the first switch is used to change over to a slower time constant so as not to corrupt the threshold voltage that is to be ascertained. In a normal mode, the stored threshold voltage is, then, used to distinguish between the states coded in an input signal. In such a context, the slower time constant is valid in the normal mode.

Abstract: A multiplier circuit has an analog multiplier with two signal inputs. A respective switching device is connected to each one of the two signal inputs of the analog multiplier for periodically reversing the polarity of the input voltages. A clock signal that can be fed to the switching devices has a changeover frequency that is preferably greater than or equal to twice the useful signal frequency. This suppresses offset-governed crosstalk of the input signals to the output of the analog multiplier. This principle can also be employed in quadricorrelators.