Patents by Inventor Emmanuel Augendre
Emmanuel Augendre has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11848191Abstract: Producing a semiconductor or piezoelectric on-insulator type substrate for RF applications which is provided with a porous layer under the BOX layer and under a layer of polycrystalline semiconductor material.Type: GrantFiled: December 15, 2021Date of Patent: December 19, 2023Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Emmanuel Augendre, Shay Reboh, Pablo Acosta Alba, Thomas Lorne, Emmanuel Rolland
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Patent number: 11688811Abstract: A field-effect transistor including an active zone comprises a source, a channel, a drain and a control gate, which is positioned level with the channel, allowing a current to flow through the channel between the source and drain along an x-axis, the channel comprising: a first edge of separation with the source; and a second edge of separation with the drain; the channel being compressively or tensilely strained, wherein the channel includes a localized perforation or a set of localized perforations along at least the first and/or second edge of the channel so as to also create at least one shear strain in the channel. A process for fabricating the transistor is provided.Type: GrantFiled: December 16, 2020Date of Patent: June 27, 2023Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Emmanuel Augendre, Maxime Argoud, Sylvain Maitrejean, Pierre Morin, Raluca Tiron
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Publication number: 20220359272Abstract: A semiconductor structure for radio frequency applications includes a support substrate made of silicon and comprising a mesoporous layer, a dielectric layer arranged on the mesoporous layer and a superficial layer arranged on the dielectric layer. The mesoporous layer comprises hollow pores, the internal walls of which are mainly lined with oxide. The mesoporous layer has a thickness between 3 and 40 microns and a resistivity greater than 20 kohm.cm over its entire thickness. The support substrate has a resistivity between 0.5 and 4 ohm.cm. The invention also relates to a method for producing such a semiconductor structure.Type: ApplicationFiled: March 25, 2020Publication date: November 10, 2022Inventors: Emmanuel Augendre, Frédéric Gaillard, Thomas Lorne, Emmanuel Rolland, Christelle Veytizou, Isabelle Bertrand, Frédéric Allibert
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Patent number: 11469137Abstract: A method for manufacturing a semiconductor-on-insulator type substrate for radiofrequency applications is provided, including the steps of: directly bonding a support substrate of a single crystal material and a donor substrate including a thin layer of a semiconductor material, one or more layers of dielectric material being at a bonding interface thereof; transferring the thin layer onto the support substrate; and forming an electric charge trap region in the support substrate in contact with the one or more layers of the dielectric material present at the bonding interface, by transforming a buried zone of the support substrate into a polycrystal.Type: GrantFiled: December 16, 2020Date of Patent: October 11, 2022Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Shay Reboh, Pablo Acosta Alba, Emmanuel Augendre
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Patent number: 11450755Abstract: An electronic device is provided, including a transistor and a substrate surmounted by first through third elements, the second element being arranged between the first and the third elements and including a nano-object, a transistor channel area being formed by part of the nano-object, a first end of the nano-object being connected to the first element by a first electrode including a first part forming a first continuity of matter and a second part formed on the first part, a second end of the nano-object being connected to the third element by a second electrode including a first part forming a second continuity of matter and a second part formed on the first part, such that a lattice parameter of the second part is suited to a lattice parameter of the first part to induce a stress in the nano-object along a reference axis.Type: GrantFiled: June 17, 2020Date of Patent: September 20, 2022Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Shay Reboh, Emmanuel Augendre, Remi Coquand, Nicolas Loubet
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Publication number: 20220189994Abstract: Producing a semiconductor or piezoelectric on-insulator type substrate for RF applications which is provided with a porous layer under the BOX layer and under a layer of polycrystalline semiconductor material.Type: ApplicationFiled: December 15, 2021Publication date: June 16, 2022Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Emmanuel Augendre, Shay Reboh, Pablo Acosta Alba, Thomas Lorne, Emmanuel Rolland
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Publication number: 20220148908Abstract: The invention relates to a method of forming a trapping structure of a useful substrate designed to trap charges and limit at least one of crosstalk, radio frequency losses, and distortions of a device that may be formed on or in the useful substrate. Formation of the trapping structure includes forming a first layer that includes amorphous silicon carbide and forming a second layer covering the first layer that comprises an insulating or semiconductor material in an amorphous state and having a crystallisation temperature lower than that of the amorphous silicon carbide.Type: ApplicationFiled: November 9, 2021Publication date: May 12, 2022Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Emmanuel Augendre, François Andrieu, Cédric Taillandier
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Publication number: 20210183690Abstract: A method for manufacturing a semiconductor-on-insulator type substrate for radiofrequency applications is provided, including the steps of: directly bonding a support substrate of a single crystal material and a donor substrate including a thin layer of a semiconductor material, one or more layers of dielectric material being at a bonding interface thereof; transferring the thin layer onto the support substrate; and forming an electric charge trap region in the support substrate in contact with the one or more layers of the dielectric material present at the bonding interface, by transforming a buried zone of the support substrate into a polycrystal.Type: ApplicationFiled: December 16, 2020Publication date: June 17, 2021Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Shay REBOH, Pablo ACOSTA ALBA, Emmanuel AUGENDRE
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Patent number: 10978594Abstract: The invention relates to a field-effect transistor including an active zone including a source, a channel, a drain and a control gate, which is positioned level with said channel, allowing a current to flow through said channel between the source and drain along an x-axis, said channel including: a first edge of separation with said source; and a second edge of separation with said drain; said channel being compressively or tensilely strained, characterized in that said channel includes a localized perforation or a set of localized perforations along at least said first and/or second edge of said channel so as to also create at least one shear strain in said channel. The invention also relates to a process for fabricating said transistor.Type: GrantFiled: December 22, 2015Date of Patent: April 13, 2021Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Emmanuel Augendre, Maxime Argoud, Sylvain Maitrejean, Pierre Morin, Raluca Tiron
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Publication number: 20210104634Abstract: A field-effect transistor including an active zone comprises a source, a channel, a drain and a control gate, which is positioned level with the channel, allowing a current to flow through the channel between the source and drain along an x-axis, the channel comprising: a first edge of separation with the source; and a second edge of separation with the drain; the channel being compressively or tensilely strained, wherein the channel includes a localized perforation or a set of localized perforations along at least the first and/or second edge of the channel so as to also create at least one shear strain in the channel. A process for fabricating the transistor is provided.Type: ApplicationFiled: December 16, 2020Publication date: April 8, 2021Inventors: Emmanuel AUGENDRE, Maxime ARGOUD, Sylvain MAITREJEAN, Pierre MORIN, Raluca TIRON
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Patent number: 10818775Abstract: The method for fabricating a field-effect transistor comprises a step of producing a sacrificial gate and first and second spacers covering first, second and third parts of successive first to fifth semiconductor nanowires of a stack. The fabricating method comprises a step of forming a channel area of the transistor, which channel area is compressively stressed and distinct from the second part of the third nanowire. The channel area is connected to a source electrode of the transistor by the first part of the second nanowire, and to a drain electrode of the transistor by the third part of the second nanowire.Type: GrantFiled: November 14, 2018Date of Patent: October 27, 2020Assignees: Commissariat a l'energie atomique et aux energies alternatives, International Business Machines CorporationInventors: Shay Reboh, Emmanuel Augendre, Remi Coquand, Nicolas Loubet
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Publication number: 20200321452Abstract: An electronic device is provided, including a transistor, a substrate surmounted by first, second, and third elements, the second arranged between the first and the third and including a nano-object, a channel area of the transistor formed by part of the nano-object, the nano-object including first and second opposite ends along a reference axis passing through the ends, the first end connected to the first element via a first electrode including a first part and a second part formed on the first part, the second end connected to the third element via a second electrode including a first part and a second part formed on the first part, the first parts formed of a first material and the second parts formed of a second material, a lattice parameter of the second material suited to that of the first material to induce a stress in the nano-object along the reference axis.Type: ApplicationFiled: June 17, 2020Publication date: October 8, 2020Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Shay REBOH, Emmanuel AUGENDRE, Remi COQUAND, Nicolas LOUBET
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Patent number: 10727320Abstract: A method of manufacturing a field effect transistor is provided, including supplying a substrate surmounted by first, second, and third structures, the second structure arranged between the first and the third structures and including at least one first nano-object located away from the substrate, a part of the first nano-object being configured to form a channel area of the transistor; forming electrodes of the transistor including epitaxial growth of a first material to obtain a first continuity of matter made of the first material between the second structure and the first structure, and to obtain a second continuity of matter made of the first material between the second structure and the third structure; and epitaxial growth of a second material, starting from the first material, the second material having a lattice parameter different from a lattice parameter of the first material of the first and the second continuities.Type: GrantFiled: December 29, 2017Date of Patent: July 28, 2020Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Shay Reboh, Emmanuel Augendre, Remi Coquand, Nicolas Loubet
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Patent number: 10714392Abstract: Techniques for optimizing junctions of a gate-all-around nanosheet device are provided. In one aspect, a method of forming a nanosheet device includes: forming an alternating series of first/second nanosheets including a first/second material as a stack on a wafer; forming a dummy gate(s) on the stack; patterning the stack into a fin stack(s) beneath the dummy gate(s); etching the fin stack(s) to selectively pull back the second nanosheets in the fin stack(s) forming pockets in the fin stack(s); filling the pockets with a strain-inducing material; burying the dummy gate(s) in a dielectric material; selectively removing the dummy gate(s) forming a gate trench(es) in the dielectric material; selectively removing either the first nanosheets or the second nanosheets from the fin stack(s); and forming a replacement gate(s) in the gate trench(es). A nanosheet device is also provided.Type: GrantFiled: July 18, 2018Date of Patent: July 14, 2020Assignee: International Business Machines CorporationInventors: Nicolas Loubet, Emmanuel Augendre, Remi Coquand, Shay Reboh
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Patent number: 10665497Abstract: The method of manufacturing a structure comprising one or several strained semiconducting zones capable of forming one or several transistor channel regions, the method including the following steps: a) providing a substrate coated with a masking layer wherein there are one or several first slits exposing one or several first oblong semiconducting portions made of a first semiconducting material and extending in a first direction, b) making a second semiconducting material grow with a mesh parameter different from the mesh parameter of the first semiconducting material, so as to form one or several first semiconducting blocks strained along the first direction, on said one or several first oblong semiconducting portions.Type: GrantFiled: March 13, 2017Date of Patent: May 26, 2020Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMICROELECTRONICS IncInventors: Emmanuel Augendre, Nicolas Loubet, Sylvain Maitrejean, Pierre Morin
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Patent number: 10600786Abstract: Manufacture of a transistor device with at least one P type transistor with channel structure strained in uniaxial compression strain starting from a silicon layer strained in biaxial tension, by amorphization recrystallization then germanium condensation.Type: GrantFiled: March 7, 2017Date of Patent: March 24, 2020Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMICROELECTRONICS IncInventors: Sylvain Maitrejean, Emmanuel Augendre, Pierre Morin, Shay Reboh
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Publication number: 20200027791Abstract: Techniques for optimizing junctions of a gate-all-around nanosheet device are provided. In one aspect, a method of forming a nanosheet device includes: forming an alternating series of first/second nanosheets including a first/second material as a stack on a wafer; forming a dummy gate(s) on the stack; patterning the stack into a fin stack(s) beneath the dummy gate(s); etching the fin stack(s) to selectively pull back the second nanosheets in the fin stack(s) forming pockets in the fin stack(s); filling the pockets with a strain-inducing material; burying the dummy gate(s) in a dielectric material; selectively removing the dummy gate(s) forming a gate trench(es) in the dielectric material; selectively removing either the first nanosheets or the second nanosheets from the fin stack(s); and forming a replacement gate(s) in the gate trench(es). A nanosheet device is also provided.Type: ApplicationFiled: July 18, 2018Publication date: January 23, 2020Inventors: Nicolas Loubet, Emmanuel Augendre, Remi Coquand, Shay Reboh
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Patent number: 10431683Abstract: A method for making a semiconductor device, including: a) etching a stack of a layer of a second semiconductor, which is crystalline, arranged between a substrate and a layer of a first semiconductor, which is crystalline, the second semiconductor being different from the first semiconductor and subjected to a compressive stress, forming a nanowire stack, b) making a dummy gate and outer spacers, covering a part of the nanowire stack which is formed by portions of the nanowires, c) etching the nanowire stack such that only said part of the stack is preserved, d) removing the portion of the second semiconductor nanowire, e) depositing, in a space formed by this removal, a sacrificial material portion, f) making source and drain regions and inner spacers, g) removing the dummy gate and the sacrificial material portion, h) making a gate.Type: GrantFiled: December 11, 2017Date of Patent: October 1, 2019Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Shay Reboh, Emmanuel Augendre, Remi Coquand, Nicolas Loubet
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Publication number: 20190207016Abstract: The method of manufacturing at least one field effect transistor is such that it comprises a step of supplying a substrate (1) surmounted by first, second and third structures (100, 200, 300), the second structure (200) being arranged between the first and third structures (100, 300). The second structure (200) comprises at least one first nano-object (201) located away from the substrate (1), a part (201c) of the first nano-object (201) being intended to form a channel area of the transistor.Type: ApplicationFiled: December 29, 2017Publication date: July 4, 2019Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Shay REBOH, Emmanuel Augendre, Remi Coquand, Nicolas Loubet
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Publication number: 20190157422Abstract: The method for fabricating a field-effect transistor comprises a step of producing a sacrificial gate and first and second spacers covering first, second and third parts of successive first to fifth semiconductor nanowires of a stack. The fabricating method comprises a step of forming a channel area of the transistor, which channel area is compressively stressed and distinct from the second part of the third nanowire. The channel area is connected to a source electrode of the transistor by the first part of the second nanowire, and to a drain electrode of the transistor by the third part of the second nanowire.Type: ApplicationFiled: November 14, 2018Publication date: May 23, 2019Applicants: Commissariat a l'energie atomique et aux energies alternatives, International Business Machines CorporationInventors: Shay REBOH, Emmanuel AUGENDRE, Remi COQUAND, Nicolas LOUBET