Patents by Inventor Emmanuel Augendre

Emmanuel Augendre has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10818775
    Abstract: The method for fabricating a field-effect transistor comprises a step of producing a sacrificial gate and first and second spacers covering first, second and third parts of successive first to fifth semiconductor nanowires of a stack. The fabricating method comprises a step of forming a channel area of the transistor, which channel area is compressively stressed and distinct from the second part of the third nanowire. The channel area is connected to a source electrode of the transistor by the first part of the second nanowire, and to a drain electrode of the transistor by the third part of the second nanowire.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: October 27, 2020
    Assignees: Commissariat a l'energie atomique et aux energies alternatives, International Business Machines Corporation
    Inventors: Shay Reboh, Emmanuel Augendre, Remi Coquand, Nicolas Loubet
  • Publication number: 20200321452
    Abstract: An electronic device is provided, including a transistor, a substrate surmounted by first, second, and third elements, the second arranged between the first and the third and including a nano-object, a channel area of the transistor formed by part of the nano-object, the nano-object including first and second opposite ends along a reference axis passing through the ends, the first end connected to the first element via a first electrode including a first part and a second part formed on the first part, the second end connected to the third element via a second electrode including a first part and a second part formed on the first part, the first parts formed of a first material and the second parts formed of a second material, a lattice parameter of the second material suited to that of the first material to induce a stress in the nano-object along the reference axis.
    Type: Application
    Filed: June 17, 2020
    Publication date: October 8, 2020
    Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Shay REBOH, Emmanuel AUGENDRE, Remi COQUAND, Nicolas LOUBET
  • Patent number: 10727320
    Abstract: A method of manufacturing a field effect transistor is provided, including supplying a substrate surmounted by first, second, and third structures, the second structure arranged between the first and the third structures and including at least one first nano-object located away from the substrate, a part of the first nano-object being configured to form a channel area of the transistor; forming electrodes of the transistor including epitaxial growth of a first material to obtain a first continuity of matter made of the first material between the second structure and the first structure, and to obtain a second continuity of matter made of the first material between the second structure and the third structure; and epitaxial growth of a second material, starting from the first material, the second material having a lattice parameter different from a lattice parameter of the first material of the first and the second continuities.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: July 28, 2020
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Shay Reboh, Emmanuel Augendre, Remi Coquand, Nicolas Loubet
  • Patent number: 10714392
    Abstract: Techniques for optimizing junctions of a gate-all-around nanosheet device are provided. In one aspect, a method of forming a nanosheet device includes: forming an alternating series of first/second nanosheets including a first/second material as a stack on a wafer; forming a dummy gate(s) on the stack; patterning the stack into a fin stack(s) beneath the dummy gate(s); etching the fin stack(s) to selectively pull back the second nanosheets in the fin stack(s) forming pockets in the fin stack(s); filling the pockets with a strain-inducing material; burying the dummy gate(s) in a dielectric material; selectively removing the dummy gate(s) forming a gate trench(es) in the dielectric material; selectively removing either the first nanosheets or the second nanosheets from the fin stack(s); and forming a replacement gate(s) in the gate trench(es). A nanosheet device is also provided.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: July 14, 2020
    Assignee: International Business Machines Corporation
    Inventors: Nicolas Loubet, Emmanuel Augendre, Remi Coquand, Shay Reboh
  • Patent number: 10665497
    Abstract: The method of manufacturing a structure comprising one or several strained semiconducting zones capable of forming one or several transistor channel regions, the method including the following steps: a) providing a substrate coated with a masking layer wherein there are one or several first slits exposing one or several first oblong semiconducting portions made of a first semiconducting material and extending in a first direction, b) making a second semiconducting material grow with a mesh parameter different from the mesh parameter of the first semiconducting material, so as to form one or several first semiconducting blocks strained along the first direction, on said one or several first oblong semiconducting portions.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: May 26, 2020
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMICROELECTRONICS Inc
    Inventors: Emmanuel Augendre, Nicolas Loubet, Sylvain Maitrejean, Pierre Morin
  • Patent number: 10600786
    Abstract: Manufacture of a transistor device with at least one P type transistor with channel structure strained in uniaxial compression strain starting from a silicon layer strained in biaxial tension, by amorphization recrystallization then germanium condensation.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: March 24, 2020
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMICROELECTRONICS Inc
    Inventors: Sylvain Maitrejean, Emmanuel Augendre, Pierre Morin, Shay Reboh
  • Publication number: 20200027791
    Abstract: Techniques for optimizing junctions of a gate-all-around nanosheet device are provided. In one aspect, a method of forming a nanosheet device includes: forming an alternating series of first/second nanosheets including a first/second material as a stack on a wafer; forming a dummy gate(s) on the stack; patterning the stack into a fin stack(s) beneath the dummy gate(s); etching the fin stack(s) to selectively pull back the second nanosheets in the fin stack(s) forming pockets in the fin stack(s); filling the pockets with a strain-inducing material; burying the dummy gate(s) in a dielectric material; selectively removing the dummy gate(s) forming a gate trench(es) in the dielectric material; selectively removing either the first nanosheets or the second nanosheets from the fin stack(s); and forming a replacement gate(s) in the gate trench(es). A nanosheet device is also provided.
    Type: Application
    Filed: July 18, 2018
    Publication date: January 23, 2020
    Inventors: Nicolas Loubet, Emmanuel Augendre, Remi Coquand, Shay Reboh
  • Patent number: 10431683
    Abstract: A method for making a semiconductor device, including: a) etching a stack of a layer of a second semiconductor, which is crystalline, arranged between a substrate and a layer of a first semiconductor, which is crystalline, the second semiconductor being different from the first semiconductor and subjected to a compressive stress, forming a nanowire stack, b) making a dummy gate and outer spacers, covering a part of the nanowire stack which is formed by portions of the nanowires, c) etching the nanowire stack such that only said part of the stack is preserved, d) removing the portion of the second semiconductor nanowire, e) depositing, in a space formed by this removal, a sacrificial material portion, f) making source and drain regions and inner spacers, g) removing the dummy gate and the sacrificial material portion, h) making a gate.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: October 1, 2019
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Shay Reboh, Emmanuel Augendre, Remi Coquand, Nicolas Loubet
  • Publication number: 20190207016
    Abstract: The method of manufacturing at least one field effect transistor is such that it comprises a step of supplying a substrate (1) surmounted by first, second and third structures (100, 200, 300), the second structure (200) being arranged between the first and third structures (100, 300). The second structure (200) comprises at least one first nano-object (201) located away from the substrate (1), a part (201c) of the first nano-object (201) being intended to form a channel area of the transistor.
    Type: Application
    Filed: December 29, 2017
    Publication date: July 4, 2019
    Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Shay REBOH, Emmanuel Augendre, Remi Coquand, Nicolas Loubet
  • Publication number: 20190157422
    Abstract: The method for fabricating a field-effect transistor comprises a step of producing a sacrificial gate and first and second spacers covering first, second and third parts of successive first to fifth semiconductor nanowires of a stack. The fabricating method comprises a step of forming a channel area of the transistor, which channel area is compressively stressed and distinct from the second part of the third nanowire. The channel area is connected to a source electrode of the transistor by the first part of the second nanowire, and to a drain electrode of the transistor by the third part of the second nanowire.
    Type: Application
    Filed: November 14, 2018
    Publication date: May 23, 2019
    Applicants: Commissariat a l'energie atomique et aux energies alternatives, International Business Machines Corporation
    Inventors: Shay REBOH, Emmanuel AUGENDRE, Remi COQUAND, Nicolas LOUBET
  • Patent number: 10269930
    Abstract: Method for producing a semiconductor device, comprising: producing a stack including a first crystalline semiconductor portion intended to form a channel and arranged on at least one second portion which can be selectively etched vis-à-vis the first portion, producing a dummy gate and external spacers, etching the stack, a remaining part of the stack under the dummy gate and the external spacers being conserved, producing source/drain by epitaxy from the remaining part of the stack; removing the dummy gate and the second portion, oxidizing portions of the source/drain from the parts of the source/drain revealed by the removal of the second portion, forming internal spacers, producing a gate electrically insulated from the source/drain by the external and internal spacers.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: April 23, 2019
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Shay Reboh, Emmanuel Augendre, Remi Coquand
  • Patent number: 10256102
    Abstract: A process for fabricating a gate-wrap-around field-effect transistor is provided, including providing a substrate surmounted with first and second nanowires extending in a same longitudinal direction and having a median portion covered by a first material, and first and second ends that are arranged on either side of the median portion, a periphery of which is covered by respective first and second dielectric spacers made of a second material that is different from the first material, the ends having exposed lateral faces; doping a portion of the first and second ends via the lateral faces; depositing an amorphous silicon alloy on the first and second lateral faces followed by crystallizing the alloy; and depositing a metal on either side of the nanowires to form first and second metal contacts that respectively make electrical contact with the doped portions of the first and second ends of the nanowires.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: April 9, 2019
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Remi Coquand, Emmanuel Augendre, Shay Reboh
  • Patent number: 10217842
    Abstract: A method for making a semiconductor device, including: a) making, on a substrate, a stack comprising a first semiconductor portion able to form an active zone and arranged between two second portions of a material able to be selectively etched relative to the semiconductor of the first portion, b) making, on a part of the stack, outer spacers and a dummy gate, c) etching the second portions such that remaining parts are arranged under the dummy gate, d) partially oxidizing the remaining parts from the outer faces, forming inner spacers, e) removing the dummy gate and non-oxidized parts of the remaining parts arranged under the dummy gate, f) making a gate between the outer spacers and between the inner spacers and covering the channel.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: February 26, 2019
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Shay Reboh, Emmanuel Augendre, Remi Coquand
  • Patent number: 10217849
    Abstract: Method for making a semiconductor device, comprising: a) making of a stack of crystalline semiconductor layers comprising a first layer and a second layer capable of being selectively etched in relation to the first layer, b) etching of part of the stack, a portion of the first layer forms a nanowire (132) arranged on the second layer, c) selective etching of second layer, d) making, beneath the nanowire, of a sacrificial portion which has an etching selectivity which is greater than that of the second layer, e) making of a sacrificial gate and of an external spacer surrounding the sacrificial gate, f) etching of the stack, revealing ends of the nanowire and of the sacrificial portion aligned with the external spacer, g) selective etching of parts of the sacrificial portion, from its ends, forming aligned cavities beneath the external spacer, h) making of an internal spacer within the cavities.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: February 26, 2019
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Sylvain Barraud, Emmanuel Augendre, Remi Coquand, Shay Reboh
  • Patent number: 10147788
    Abstract: A process for fabricating a gate-wrap-around field-effect transistor is provided, including: providing a superposition of first to third nanowires, each made of a semiconductor, the second nanowire being subjected to a strain along its longitudinal axis, a median portion of the first to third nanowires being covered by a sacrificial gate; forming voids by removing a portion of the first and third nanowires that is intermediate between their ends and their median portion, while preserving the superposition of the first to third nanowires level with the ends and under the sacrificial gate; forming an electrical insulator in the voids around the second nanowire; removing the sacrificial gate and the median portion of the first and third nanowires; and forming a gate electrode wrapped around the median portion of the second nanowire.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: December 4, 2018
    Assignee: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Emmanuel Augendre, Remi Coquand, Shay Reboh
  • Patent number: 10141424
    Abstract: Method of manufacturing a structure with semiconducting bars suitable for forming one at least one transistor channel, including the following steps: a) make a semiconducting structure, composed of an alternation of first bars based on a first material and second bars based on a second material, the second material being a semiconducting material, then b) remove exposed portions of the structure based on the first material through an opening in a mask formed on the structure, the removal being made by selective etching in the opening of the first material relative to the second material, so as to expose a space around the second bars, then c) grow a given semiconducting material (25) around the second bars (6c) in the opening, the given semiconducting material having a mesh parameter different from the mesh parameter of the second material (7) so as to induce a strain on the sheaths based on the given semiconducting material.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: November 27, 2018
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, IBM CORPORATION
    Inventors: Remi Coquand, Emmanuel Augendre, Nicolas Loubet, Shay Reboh
  • Patent number: 10134875
    Abstract: The invention relates to a process for fabricating a vertical transistor, comprising the step of providing a substrate surmounted by a stack of first, second and third layers made of first, second and third semiconductors, respectively, said second semiconductor being different from the first and third semiconductors. The process further includes horizontally growing first, second and third dielectric layers, by oxidation, from the first, second and third semiconductor layers, respectively, with a second dielectric layer, the thickness of which differs from the thickness of said first and third dielectric layers and removing the second dielectric layer so as to form a recess that is vertically self-aligned with the second semiconductor layer, which recess is positioned vertically between first and second blocks that are made facing the first and third semiconductor layers. Finally, the process includes forming a gate stack in said self-aligned recess.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: November 20, 2018
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Shay Reboh, Emmanuel Augendre, Remi Coquand
  • Patent number: 10109735
    Abstract: A process for fabricating a gate-wrap-around field-effect transistor is provided, including: providing a superposition of first to third nanowires, each made of a semiconductor, the second nanowire being subjected to a strain along its longitudinal axis, a median portion of the first to third nanowires being covered by a sacrificial gate; forming voids by removing a portion of the first and third nanowires that is intermediate between their ends and their median portion, while preserving the superposition of the first to third nanowires level with the ends and under the sacrificial gate; forming an electrical insulator in the voids around the second nanowire; removing the sacrificial gate and the median portion of the first and third nanowires; and forming a gate electrode wrapped around the median portion of the second nanowire.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: October 23, 2018
    Assignee: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Remi Coquand, Emmanuel Augendre, Shay Reboh
  • Publication number: 20180301341
    Abstract: A process for fabricating a gate-wrap-around field-effect transistor is provided, including providing a substrate surmounted with first and second nanowires extending in a same longitudinal direction and having a median portion covered by a first material, and first and second ends that are arranged on either side of the median portion, a periphery of which is covered by respective first and second dielectric spacers made of a second material that is different from the first material, the ends having exposed lateral faces; doping a portion of the first and second ends via the lateral faces; depositing an amorphous silicon alloy on the first and second lateral faces followed by crystallizing the alloy; and depositing a metal on either side of the nanowires to form first and second metal contacts that respectively make electrical contact with the doped portions of the first and second ends of the nanowires.
    Type: Application
    Filed: March 28, 2018
    Publication date: October 18, 2018
    Applicant: Commissariat a l'energie atomique et aux energies alternatives
    Inventors: Remi COQUAND, Emmanuel AUGENDRE, Shay REBOH
  • Patent number: 10096694
    Abstract: A process for fabricating a vertical transistor is provided, including steps of providing a substrate surmounted by a stack of first to third layers made of first to third semiconductors materials of two different types; partially etching the first and third layers with an etching that is selective, so as to form a first void in the first layer and a third void in the third layer, extending to the lower surface and to the upper surface of the second layer, respectively; filling the voids in order to form spacers making contact with the lower surface and the upper surface, respectively; partially etching the second layer with an etching that is selective, so as to form a second void between the first and second spacers; and depositing a conductor material in the second void.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: October 9, 2018
    Assignee: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Remi Coquand, Emmanuel Augendre, Shay Reboh