Patents by Inventor Emmanuel Augendre

Emmanuel Augendre has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220189994
    Abstract: Producing a semiconductor or piezoelectric on-insulator type substrate for RF applications which is provided with a porous layer under the BOX layer and under a layer of polycrystalline semiconductor material.
    Type: Application
    Filed: December 15, 2021
    Publication date: June 16, 2022
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Emmanuel Augendre, Shay Reboh, Pablo Acosta Alba, Thomas Lorne, Emmanuel Rolland
  • Publication number: 20220148908
    Abstract: The invention relates to a method of forming a trapping structure of a useful substrate designed to trap charges and limit at least one of crosstalk, radio frequency losses, and distortions of a device that may be formed on or in the useful substrate. Formation of the trapping structure includes forming a first layer that includes amorphous silicon carbide and forming a second layer covering the first layer that comprises an insulating or semiconductor material in an amorphous state and having a crystallisation temperature lower than that of the amorphous silicon carbide.
    Type: Application
    Filed: November 9, 2021
    Publication date: May 12, 2022
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Emmanuel Augendre, François Andrieu, Cédric Taillandier
  • Publication number: 20210183690
    Abstract: A method for manufacturing a semiconductor-on-insulator type substrate for radiofrequency applications is provided, including the steps of: directly bonding a support substrate of a single crystal material and a donor substrate including a thin layer of a semiconductor material, one or more layers of dielectric material being at a bonding interface thereof; transferring the thin layer onto the support substrate; and forming an electric charge trap region in the support substrate in contact with the one or more layers of the dielectric material present at the bonding interface, by transforming a buried zone of the support substrate into a polycrystal.
    Type: Application
    Filed: December 16, 2020
    Publication date: June 17, 2021
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Shay REBOH, Pablo ACOSTA ALBA, Emmanuel AUGENDRE
  • Patent number: 10978594
    Abstract: The invention relates to a field-effect transistor including an active zone including a source, a channel, a drain and a control gate, which is positioned level with said channel, allowing a current to flow through said channel between the source and drain along an x-axis, said channel including: a first edge of separation with said source; and a second edge of separation with said drain; said channel being compressively or tensilely strained, characterized in that said channel includes a localized perforation or a set of localized perforations along at least said first and/or second edge of said channel so as to also create at least one shear strain in said channel. The invention also relates to a process for fabricating said transistor.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: April 13, 2021
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Emmanuel Augendre, Maxime Argoud, Sylvain Maitrejean, Pierre Morin, Raluca Tiron
  • Publication number: 20210104634
    Abstract: A field-effect transistor including an active zone comprises a source, a channel, a drain and a control gate, which is positioned level with the channel, allowing a current to flow through the channel between the source and drain along an x-axis, the channel comprising: a first edge of separation with the source; and a second edge of separation with the drain; the channel being compressively or tensilely strained, wherein the channel includes a localized perforation or a set of localized perforations along at least the first and/or second edge of the channel so as to also create at least one shear strain in the channel. A process for fabricating the transistor is provided.
    Type: Application
    Filed: December 16, 2020
    Publication date: April 8, 2021
    Inventors: Emmanuel AUGENDRE, Maxime ARGOUD, Sylvain MAITREJEAN, Pierre MORIN, Raluca TIRON
  • Patent number: 10818775
    Abstract: The method for fabricating a field-effect transistor comprises a step of producing a sacrificial gate and first and second spacers covering first, second and third parts of successive first to fifth semiconductor nanowires of a stack. The fabricating method comprises a step of forming a channel area of the transistor, which channel area is compressively stressed and distinct from the second part of the third nanowire. The channel area is connected to a source electrode of the transistor by the first part of the second nanowire, and to a drain electrode of the transistor by the third part of the second nanowire.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: October 27, 2020
    Assignees: Commissariat a l'energie atomique et aux energies alternatives, International Business Machines Corporation
    Inventors: Shay Reboh, Emmanuel Augendre, Remi Coquand, Nicolas Loubet
  • Publication number: 20200321452
    Abstract: An electronic device is provided, including a transistor, a substrate surmounted by first, second, and third elements, the second arranged between the first and the third and including a nano-object, a channel area of the transistor formed by part of the nano-object, the nano-object including first and second opposite ends along a reference axis passing through the ends, the first end connected to the first element via a first electrode including a first part and a second part formed on the first part, the second end connected to the third element via a second electrode including a first part and a second part formed on the first part, the first parts formed of a first material and the second parts formed of a second material, a lattice parameter of the second material suited to that of the first material to induce a stress in the nano-object along the reference axis.
    Type: Application
    Filed: June 17, 2020
    Publication date: October 8, 2020
    Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Shay REBOH, Emmanuel AUGENDRE, Remi COQUAND, Nicolas LOUBET
  • Patent number: 10727320
    Abstract: A method of manufacturing a field effect transistor is provided, including supplying a substrate surmounted by first, second, and third structures, the second structure arranged between the first and the third structures and including at least one first nano-object located away from the substrate, a part of the first nano-object being configured to form a channel area of the transistor; forming electrodes of the transistor including epitaxial growth of a first material to obtain a first continuity of matter made of the first material between the second structure and the first structure, and to obtain a second continuity of matter made of the first material between the second structure and the third structure; and epitaxial growth of a second material, starting from the first material, the second material having a lattice parameter different from a lattice parameter of the first material of the first and the second continuities.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: July 28, 2020
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Shay Reboh, Emmanuel Augendre, Remi Coquand, Nicolas Loubet
  • Patent number: 10714392
    Abstract: Techniques for optimizing junctions of a gate-all-around nanosheet device are provided. In one aspect, a method of forming a nanosheet device includes: forming an alternating series of first/second nanosheets including a first/second material as a stack on a wafer; forming a dummy gate(s) on the stack; patterning the stack into a fin stack(s) beneath the dummy gate(s); etching the fin stack(s) to selectively pull back the second nanosheets in the fin stack(s) forming pockets in the fin stack(s); filling the pockets with a strain-inducing material; burying the dummy gate(s) in a dielectric material; selectively removing the dummy gate(s) forming a gate trench(es) in the dielectric material; selectively removing either the first nanosheets or the second nanosheets from the fin stack(s); and forming a replacement gate(s) in the gate trench(es). A nanosheet device is also provided.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: July 14, 2020
    Assignee: International Business Machines Corporation
    Inventors: Nicolas Loubet, Emmanuel Augendre, Remi Coquand, Shay Reboh
  • Patent number: 10665497
    Abstract: The method of manufacturing a structure comprising one or several strained semiconducting zones capable of forming one or several transistor channel regions, the method including the following steps: a) providing a substrate coated with a masking layer wherein there are one or several first slits exposing one or several first oblong semiconducting portions made of a first semiconducting material and extending in a first direction, b) making a second semiconducting material grow with a mesh parameter different from the mesh parameter of the first semiconducting material, so as to form one or several first semiconducting blocks strained along the first direction, on said one or several first oblong semiconducting portions.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: May 26, 2020
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMICROELECTRONICS Inc
    Inventors: Emmanuel Augendre, Nicolas Loubet, Sylvain Maitrejean, Pierre Morin
  • Patent number: 10600786
    Abstract: Manufacture of a transistor device with at least one P type transistor with channel structure strained in uniaxial compression strain starting from a silicon layer strained in biaxial tension, by amorphization recrystallization then germanium condensation.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: March 24, 2020
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMICROELECTRONICS Inc
    Inventors: Sylvain Maitrejean, Emmanuel Augendre, Pierre Morin, Shay Reboh
  • Publication number: 20200027791
    Abstract: Techniques for optimizing junctions of a gate-all-around nanosheet device are provided. In one aspect, a method of forming a nanosheet device includes: forming an alternating series of first/second nanosheets including a first/second material as a stack on a wafer; forming a dummy gate(s) on the stack; patterning the stack into a fin stack(s) beneath the dummy gate(s); etching the fin stack(s) to selectively pull back the second nanosheets in the fin stack(s) forming pockets in the fin stack(s); filling the pockets with a strain-inducing material; burying the dummy gate(s) in a dielectric material; selectively removing the dummy gate(s) forming a gate trench(es) in the dielectric material; selectively removing either the first nanosheets or the second nanosheets from the fin stack(s); and forming a replacement gate(s) in the gate trench(es). A nanosheet device is also provided.
    Type: Application
    Filed: July 18, 2018
    Publication date: January 23, 2020
    Inventors: Nicolas Loubet, Emmanuel Augendre, Remi Coquand, Shay Reboh
  • Patent number: 10431683
    Abstract: A method for making a semiconductor device, including: a) etching a stack of a layer of a second semiconductor, which is crystalline, arranged between a substrate and a layer of a first semiconductor, which is crystalline, the second semiconductor being different from the first semiconductor and subjected to a compressive stress, forming a nanowire stack, b) making a dummy gate and outer spacers, covering a part of the nanowire stack which is formed by portions of the nanowires, c) etching the nanowire stack such that only said part of the stack is preserved, d) removing the portion of the second semiconductor nanowire, e) depositing, in a space formed by this removal, a sacrificial material portion, f) making source and drain regions and inner spacers, g) removing the dummy gate and the sacrificial material portion, h) making a gate.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: October 1, 2019
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Shay Reboh, Emmanuel Augendre, Remi Coquand, Nicolas Loubet
  • Publication number: 20190207016
    Abstract: The method of manufacturing at least one field effect transistor is such that it comprises a step of supplying a substrate (1) surmounted by first, second and third structures (100, 200, 300), the second structure (200) being arranged between the first and third structures (100, 300). The second structure (200) comprises at least one first nano-object (201) located away from the substrate (1), a part (201c) of the first nano-object (201) being intended to form a channel area of the transistor.
    Type: Application
    Filed: December 29, 2017
    Publication date: July 4, 2019
    Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Shay REBOH, Emmanuel Augendre, Remi Coquand, Nicolas Loubet
  • Publication number: 20190157422
    Abstract: The method for fabricating a field-effect transistor comprises a step of producing a sacrificial gate and first and second spacers covering first, second and third parts of successive first to fifth semiconductor nanowires of a stack. The fabricating method comprises a step of forming a channel area of the transistor, which channel area is compressively stressed and distinct from the second part of the third nanowire. The channel area is connected to a source electrode of the transistor by the first part of the second nanowire, and to a drain electrode of the transistor by the third part of the second nanowire.
    Type: Application
    Filed: November 14, 2018
    Publication date: May 23, 2019
    Applicants: Commissariat a l'energie atomique et aux energies alternatives, International Business Machines Corporation
    Inventors: Shay REBOH, Emmanuel AUGENDRE, Remi COQUAND, Nicolas LOUBET
  • Patent number: 10269930
    Abstract: Method for producing a semiconductor device, comprising: producing a stack including a first crystalline semiconductor portion intended to form a channel and arranged on at least one second portion which can be selectively etched vis-à-vis the first portion, producing a dummy gate and external spacers, etching the stack, a remaining part of the stack under the dummy gate and the external spacers being conserved, producing source/drain by epitaxy from the remaining part of the stack; removing the dummy gate and the second portion, oxidizing portions of the source/drain from the parts of the source/drain revealed by the removal of the second portion, forming internal spacers, producing a gate electrically insulated from the source/drain by the external and internal spacers.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: April 23, 2019
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Shay Reboh, Emmanuel Augendre, Remi Coquand
  • Patent number: 10256102
    Abstract: A process for fabricating a gate-wrap-around field-effect transistor is provided, including providing a substrate surmounted with first and second nanowires extending in a same longitudinal direction and having a median portion covered by a first material, and first and second ends that are arranged on either side of the median portion, a periphery of which is covered by respective first and second dielectric spacers made of a second material that is different from the first material, the ends having exposed lateral faces; doping a portion of the first and second ends via the lateral faces; depositing an amorphous silicon alloy on the first and second lateral faces followed by crystallizing the alloy; and depositing a metal on either side of the nanowires to form first and second metal contacts that respectively make electrical contact with the doped portions of the first and second ends of the nanowires.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: April 9, 2019
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Remi Coquand, Emmanuel Augendre, Shay Reboh
  • Patent number: 10217842
    Abstract: A method for making a semiconductor device, including: a) making, on a substrate, a stack comprising a first semiconductor portion able to form an active zone and arranged between two second portions of a material able to be selectively etched relative to the semiconductor of the first portion, b) making, on a part of the stack, outer spacers and a dummy gate, c) etching the second portions such that remaining parts are arranged under the dummy gate, d) partially oxidizing the remaining parts from the outer faces, forming inner spacers, e) removing the dummy gate and non-oxidized parts of the remaining parts arranged under the dummy gate, f) making a gate between the outer spacers and between the inner spacers and covering the channel.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: February 26, 2019
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Shay Reboh, Emmanuel Augendre, Remi Coquand
  • Patent number: 10217849
    Abstract: Method for making a semiconductor device, comprising: a) making of a stack of crystalline semiconductor layers comprising a first layer and a second layer capable of being selectively etched in relation to the first layer, b) etching of part of the stack, a portion of the first layer forms a nanowire (132) arranged on the second layer, c) selective etching of second layer, d) making, beneath the nanowire, of a sacrificial portion which has an etching selectivity which is greater than that of the second layer, e) making of a sacrificial gate and of an external spacer surrounding the sacrificial gate, f) etching of the stack, revealing ends of the nanowire and of the sacrificial portion aligned with the external spacer, g) selective etching of parts of the sacrificial portion, from its ends, forming aligned cavities beneath the external spacer, h) making of an internal spacer within the cavities.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: February 26, 2019
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Sylvain Barraud, Emmanuel Augendre, Remi Coquand, Shay Reboh
  • Patent number: 10147788
    Abstract: A process for fabricating a gate-wrap-around field-effect transistor is provided, including: providing a superposition of first to third nanowires, each made of a semiconductor, the second nanowire being subjected to a strain along its longitudinal axis, a median portion of the first to third nanowires being covered by a sacrificial gate; forming voids by removing a portion of the first and third nanowires that is intermediate between their ends and their median portion, while preserving the superposition of the first to third nanowires level with the ends and under the sacrificial gate; forming an electrical insulator in the voids around the second nanowire; removing the sacrificial gate and the median portion of the first and third nanowires; and forming a gate electrode wrapped around the median portion of the second nanowire.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: December 4, 2018
    Assignee: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Emmanuel Augendre, Remi Coquand, Shay Reboh