Abstract: A device for simultaneously carrying out an electro-chemical and a topographical near field microscopy is described, which device comprises a region for topographical near field measurement and a region for electrochemical near field measurement, with the region for topographical near field measurement extending completely as far as to the immediate tip of the arrangement, characterized in that the region for electrochemical near field measurement starts at a defined distance from the immediate tip.

Abstract: A dynamic random access memory capacitor and to a method for producing the same are described. A first (bottom) electrode of the capacitor has a grained surface made of tungsten silicide placed on a tungsten silicide layer which is disposed near a surface of a electrode body. The graining of the tungsten silicide layer is formed by tempering a temporarily present double layer that is formed of an understoichiometric tungsten silicide layer and a silicon layer. The double layer is formed on the tungsten silicide layer.

Abstract: A method of producing a device for simultaneously carrying out an electrochemical and a topographical near field microscopy is disclosed, which is characterised in that a probe suitable for topographic near field microscopy is covered by a conductive material, the conductive material is covered by an insulating layer, and the conductive material and the insulating layer are removed in the region of the immediate tip of the probe.

Abstract: Memory cells each include one transistor and one capacitor. A memory node of the capacitor is disposed in a first indentation, while a gate electrode of the transistor is disposed in a second indentation. An upper source/drain region, a channel region, and a lower source/drain region of the transistor are disposed above one another and each adjoin both a first flank of the first indentation and the second indentation. At least a portion of the first flank is provided with a capacitor dielectric, which in the region of the lower source/drain region has a recess, in which the memory node adjoins the lower source/drain region. The second indentation of a first one of the memory cells can adjoin the memory node that is disposed in the first indentation of a second one of the memory cells. The second indentations can be parts of word line trenches, which extend transversely to insulation trenches.

Abstract: A memory cell array has memory cells in which there is an electrical connection between a polycrystalline semiconductor material of a capacitor electrode and a monocrystalline semiconductor region. Islands made of an amorphous material are disposed in a vicinity of the electrical connection between the polycrystalline semiconductor material and the monocrystalline semiconductor region. The islands are produced in particular by thermally breaking up an amorphous layer which has been formed by thermal oxidation. The memory cell array is in particular a DRAM array with a trench capacitor.

Abstract: An integrated circuit having at least two vertical MOS transistors, and method for manufacturing same, wherein first source/drain regions of the two vertical MOS transistors are located in an upper region of sidewalls of a trench. A second source/drain region is shared by both MOS transistors and is adjacent at a floor of the trench. Gate electrodes of the MOS transistors that are arranged at the sidewalls of the trench can be individually contacted via parts of a conductive layer that are arranged above the first source/drain regions. In a manufacturing method, such arrangement is made possible by the deposition of a conductive layer of doped polysilicon before the generation of the trench. The area of an MOS transistor can amount to 4F2.

Abstract: An integrated circuit having at least two vertical MOS transistors, and method for manufacturing same, wherein first source/drain regions of the two vertical MOS transistors are located in an upper region of sidewalls of a trench. A second source/drain region is shared by both MOS transistors and is adjacent at a floor of the trench. Gate electrodes of the MOS transistors that are arranged at the sidewalls of the trench can be individually contacted via parts of a conductive layer that are arranged above the first source/drain regions. In a manufacturing method, such arrangement is made possible by the deposition of a conductive layer of doped polysilicon before the generation of the trench. The area of an MOS transistor can amount to 4F2.

Abstract: A method for fabricating a stacked capacitor in a semiconductor configuration, in which one electrode of the stacked capacitor is connected via a terminal region of a first conductivity type to a source or drain of a transistor. The semiconductor configuration having one electrode of a stacked capacitor produced by utilizing different etching rates of semiconductor layers of a second conductivity type which are doped to different extents. After the etching of the one electrode of the stacked capacitor, doping reversal of the semiconductor layers remaining after the etching operation to the first conductivity type is performed, with the result that the electrode has the same conductivity type as the terminal region and no pn junction occurs between the electrode and terminal region.

Abstract: A storage cell is described which includes a storage element whose electric resistance represents an information unit and can be influenced by a magnetic field as well as a transistor which when the information is read out allows for the corresponding storage cell to be selected from among the storage cells. To write the information unit, a write line and a bit line are provided which intersect in the area of the storage element and are able to generate the magnetic field. The storage cell is disposed between the bit line and a shared voltage supply connection. The storage cell is disposed between the bit line and the write line and the write line can coincide with a gate line that controls the transistor. The transistor is a planar or vertical transistor. The storage element and the transistor can be positioned next to or on top of each other.

Abstract: An integrated circuit having at least two vertical MOS transistors, and method for manufacturing same, wherein first source/drain regions of the two vertical MOS transistors are located in an upper region of sidewalls of a trench. A second source/drain region is shared by both MOS transistors and is adjacent a floor of the trench. Gate electrodes of the MOS transistors that are arranged at the sidewalls of the trench can be individually contacted via parts of a conductive layer that are arranged above the first source/drain regions. In a manufacturing method, such arrangement is made possible by the deposition of a conductive layer of doped polysilicon before the generation of the trench. The area of an MOS transistor can amount to 4F2.

Abstract: A dynamic random access memory capacitor and to a method for producing the same are described. A first (bottom) electrode of the capacitor has a grained surface made of tungsten silicide placed on a tungsten silicide layer which is disposed near a surface of a electrode body. The graining of the tungsten silicide layer is formed by tempering a temporarily present double layer that is formed of an understoichiometric tungsten silicide layer and a silicon layer. The double layer is formed on the tungsten silicide layer.

Abstract: A storage cell has a number of projections of a semiconductor substrate arranged in rows and columns, neighboring rows of the projections being translation-symmetrical in relation to a y-axis which extends parallel to the columns. Each of the projections has at least one first source/drain region of a selection transistor and one channel region arranged below the first source/drain region, which is surrounded by a gate electrode annularly. A storage capacitor is connected between the first source/drain region and a bit line. The bit line as well as the storage capacitor are arranged essentially above the semiconductor substrate. Second source/drain regions of selection transistors are buried in the semiconductor substrate and connected with each other. Word lines can be formed self-justified in the form of adjacent gate electrodes. The projections can be created by etching with only one mask.

Abstract: Memory cells each include one transistor and one capacitor. A memory node of the capacitor is disposed in a first indentation, while a gate electrode of the transistor is disposed in a second indentation. An upper source/drain region, a channel region, and a lower source/drain region of the transistor are disposed above one another and each adjoin both a first flank of the first indentation and the second indentation. At least a portion of the first flank is provided with a capacitor dielectric, which in the region of the lower source/drain region has a recess, in which the memory node adjoins the lower source/drain region. The second indentation of a first one of the memory cells can adjoin the memory node that is disposed in the first indentation of a second one of the memory cells. The second indentations can be parts of word line trenches, which extend transversely to insulation trenches.

Abstract: The SRAM cell arrangement comprises six MOS transistors per memory cell that are fashioned as vertical transistors. The MOS transistors are arranged at sidewalls of trenches (G1, G2, G4). Parts of the memory cell such as, for example, gate electrodes (Ga2, Ga4) or conductive structures (L3) fashioned as spacer are contacted via adjacent, horizontal, conductive structures (H5) arranged above a surface (O) of a substrate (S). Connections between parts of memory cells ensue via third conductive structures (L3) arranged at the sidewalls of the depressions and word lines (W) via diffusion regions (D2) that are adjacent to the sidewalls of the depressions within the substrate (S), via first bit lines, via second bit lines (B2) or/and via conductive structures (L1, L2, L6) that are partially arranged at different height with respect to an axis perpendicular to the surface (O). Contacts (K5) contact a plurality of parts of the MOS transistors simultaneously.

Abstract: A storage cell is described which includes a storage element whose electric resistance represents an information unit and can be influenced by a magnetic field as well as a transistor which when the information is read out allows for the corresponding storage cell to be selected from among the storage cells. To write the information unit, a write line and a bit line are provided which intersect in the area of the storage element and are able to generate the magnetic field. The storage cell is disposed between the bit line and a shared voltage supply connection. The storage cell is disposed between the bit line and the write line and the write line can coincide with a gate line that controls the transistor. The transistor is a planar or vertical transistor. The storage element and the transistor can be positioned next to or on top of each other.

Abstract: An SRAM cell arrangement which includes six MOS transistors per memory cell wherein each transistor is formed as a vertical transistors. The MOS transistors are arranged at sidewalls of trenches. Parts of the memory cell such as, for example, gate electrodes or conductive structures fashioned as spacers are contacted via adjacent, horizontal, conductive structures arranged above a surface of a substrate. Connections between parts of memory cells occur via third conductive structures arranged at the sidewalls of the depressions and word lines via diffusion regions that are adjacent to the sidewalls of the depressions within the substrate, via first bit lines, via second bit lines and/or via conductive structures that are partially arranged at different heights with respect to an axis perpendicular to the surface. Contacts contact a plurality of parts of the MOS transistors simultaneously.

Abstract: A read-only memory cell device includes a substrate formed of semiconductor material and having a main area. Memory cells in the vicinity of the main area are disposed in matrix form in columns and rows in a cell field. Each memory cell has in each case at least one MOS transistor with a source region, a drain region, a channel region, a gate dielectric and a gate electrode. The MOS transistors of a column are connected in series one after the other. Each column is connected to a bit line and the gate electrodes of the MOS transistors of a row are connected to a word line. The source and drain regions of the MOS transistors of a column are formed in source/drain webs running substantially parallel to one another at a predetermined spacing, are electrically insulated from one another, are produced from the semiconductor material of the substrate and have a predetermined web depth, starting from the main area of the substrate.

Abstract: An element that prevents the formation of a channel is arranged in a level of the channel region (Kaa) at one of two opposite sidewalls of a semiconductor structure that has a source/drain region (S/D1a) and a channel region (Kaa) of a vertical selection transistor arranged therebelow. The source/drain region as well as a respective word line (W1a) adjoin at both sidewalls. For folded bit lines (B1a), respectively two word lines (W1a) can be formed in the trenches (G2a). The elements of semiconductor structures neighboring along one of the trenches (G2a) are then arranged in alternation at a sidewall of the trench (G2a) and at a sidewall of a neighboring trench (D2a). A storage capacitor can be arranged over a substrate (1a) or can be buried in the substrate (1a). The connection of the selection transistor to a bit line (B1a) can ensue in many ways.

Abstract: The memory cell configuration comprises vertical transistors which are connected in a NOR architecture. The vertical transistors are disposed on flanks of trenches. Each vertical transistor includes an electrically insulated floating gate electrode, whose charge can be varied by Fowler-Nordheim tunneling due to a voltage drop between a control gate electrode and a source/drain region. The length of a coupling area in a direction parallel to a channel width, between the control gate electrode and the floating gate electrode is less than the channel width, in order to reduce the operating voltage. This is achieved by thermal oxidation of parts of the flanks of the trenches. Transistors which are adjacent in a direction transverse to the trenches share bit lines. Each bit line has a lightly doped first part and a highly doped second part. The coupling area can be enlarged even further by using a strip-shaped mask, which is extended by spacers.

Abstract: A DRAM cell arrangement and method for manufacturing same, wherein a storage capacitor is connected via a first source/drain zone of a vertical selection transistor and a bit line. Since the storage capacitor and the bit line are arranged substantially above a substrate, the bit line can be manufactured of materials having high electrical conductivity, and materials having a high dielectric constant can be utilized for the storage capacitor. At least the first source/drain zone and a channel zone are parts of a projection-like semiconductor structure that is laterally limited by at least two sidewalls. A respective word line can be arranged at the two sidewalls. An element that prevents the drive of the selection transistor by this word line is arranged between the channel zone and one of the word lines.