Abstract: A payment device is provided for use in transactions such as credit purchases at a retail store. The device includes a non-volatile memory containing a set of multiple identifiers that are associated with a customer account. The multiple identifiers are also known to an agency that provides the customer account. The device further includes a processor operable to select one identifier out of the set of multiple identifiers for use with any particular transaction involving the device and the customer account. This identifier is then conveyed from the device, typically via a store terminal, to the agency that maintains the account.

Abstract: A method and apparatus are provided for monitoring a parameter such as temperature in a system such as a computer server. The method involves defining a monitoring range for the parameter. Typically, the parameter initially lies within the monitoring range. The parameter is then tracked by determining whenever the parameter exceeds an upper or lower limit of the monitoring range. If such a limit is reached, the monitoring range is adjusted to try to accommodate the parameter within the adjusted monitoring range. A time history of the monitoring range may be recorded, including details of all the adjustments of the monitoring range. This allows the behavior of the parameter to be subsequently investigated for diagnostic purposes.

Abstract: A memory system including independent power for each memory module. The memory system includes a plurality of memory modules each including a plurality of memory chips configured to store data. The memory system further includes a power conversion unit coupled to provide power to each of the plurality of memory modules via a respective power conduit. Each of the respective power conduits is electrically isolated from each other power conduit.

Abstract: A semiconductor device includes a stored device identifier that is accessible to external systems, and a stored secret key that is inaccessible to external systems. The device also includes an input, which in operation receives a system identifier, representing the system into which the device is to be incorporated, and an authorization key. An authorization unit within the device is then used for enabling or disabling the device in accordance with the values of the stored secret key, the received system identifier and the authorization key. The authorization key is typically supplied by a support center in response to being notified of the device identifier. In one embodiment, the authorization unit encrypts the system identifier using the stored secret key as the encryption key and then compares the result against the authorization key.

Abstract: A personal authorisation device wearable by a user includes an input operable to receive data for authenticating a user, a memory operable to store validation information derived from the user authentication data, and an output operable to provide an authorisation code. The device further includes a tamper detector that triggers if the device is removed from its wearer. Triggering of the tamper detector serves to disable use of the device.

Abstract: A method for managing a fault involves detecting an error, gathering data associated with the error to generate an error event, and categorizing the error event using a hierarchical organization of the error event.

Abstract: A method and apparatus are provided for controlling the power consumption of a semiconductor device such as a CPU or other form of processor that is operable to process a sequence of instructions. The device includes a monitor for checking the power consumption of the device, in order to detect any significant change in power consumption (which can cause problems for the power supply circuitry). In order to mitigate such change, one or more dummy instructions are inserted into the sequence of instructions. The dummy instructions do not affect the logical processing, but are selected in order to limit the change in power consumption. Thus if the change in power consumption represents an increase, then dummy instructions are selected that do not require much current. Conversely, if the change in power consumption represents a decrease, then dummy instructions are selected that draw a relatively large amount of current.

Abstract: A multiprocessor computer system which provides fault tolerance includes a number of processing sets. At least one of the processing sets is operable asynchronously of a second processing set. A monitor is connected to receive I/O operations output from the processing sets for identifying faulty operation of those units. The monitor is also operable to synchronise operation of the processing sets by signalling the processing sets on receipt of outputs from those units indicative of a plurality of them being at an equivalent stage of processing. The monitor provides for buffering of I/O operations output from the processing sets and for selective forwarding of those I/O operations to an external I/O bus. The processing set may be formed from a single processor or from multiple processors.

Abstract: A method and apparatus are disclosed for supplying power in electronic equipment. Thus the apparatus comprises at least one electronic component and a power supply unit that provides power to the electronic component. The power supply unit incorporates a detector that is responsive to the power output level from the power supply unit increasing beyond a predetermined limit. If this limit is breached, the power supply unit outputs a delay signal to the electronic component. This delay signal then causes the electronic component to reduce its power consumption (such as by performing dummy operations), thereby avoiding an overload on the power supply unit.

Abstract: One embodiment of the present invention provides a system that monitors a computer system using a plurality of physical sensors. The system operates by polling the plurality of physical sensors in a given sequence at a given rate, wherein each physical sensor monitors a specific physical parameter of the computer system. The system then provides a plurality of measurements from the plurality of physical sensors to a monitoring system. If a given physical sensor detects a parameter that is not within a pre-determined operating range, the system receives an interrupt from the given physical sensor. In response to receiving this interrupt, the system raises an alarm.

Abstract: A system for receiving electrical signals that use a differential signal in adjusting a slice voltage for a single-ended signal. This differential signal includes two signal lines. A first value is represented by the first signal line at a higher voltage than the second signal line, and a second value is represented by the first signal line at a lower voltage than the second signal line. The system receives the differential signal at the destination and compares it against the slice voltage to obtain a comparison. The system uses the comparison result to adjust the slice voltage, and uses the slice voltage as a reference signal in capturing the single-ended signal. Note that this single-ended signal includes a single signal line, wherein the first value is represented on this line by a voltage above the slice voltage, and the second value is represented by a voltage below the slice voltage.

Abstract: A method and apparatus are disclosed for supplying power in electronic equipment. Thus the apparatus comprises at least one electronic component and a power supply unit that provides power to the electronic component. The power supply unit incorporates a detector that is responsive to the power output level from the power supply unit increasing beyond a predetermined limit. If this limit is breached, the power supply unit outputs a delay signal to the electronic component. This delay signal then causes the electronic component to reduce its power consumption (such as by performing dummy operations), thereby avoiding an overload on the power supply unit.

Abstract: A semiconductor device includes a stored device identifier that is accessible to external systems, and a stored secret key that is inaccessible to external systems. The device also includes an input, which in operation receives a system identifier, representing the system into which the device is to be incorporated, and an authorisation key. An authorisation unit within the device is then used for enabling or disabling the device in accordance with the values of the stored secret key, the received system identifier and the authorisation key. The authorisation key is typically supplied by a support centre in response to being notified of the device identifier. In one embodiment, the authorisation unit encrypts the system identifier using the stored secret key as the encryption key and then compares the result against the authorisation key.

Abstract: A memory system including independent power for each memory module. The memory system includes a plurality of memory modules each including a plurality of memory chips configured to store data. The memory system further includes a power conversion unit coupled to provide power to each of the plurality of memory modules via a respective power conduit. Each of the respective power conduits is electrically isolated from each other power conduit.

Abstract: An integrated TDR for locating transmission line faults. An integrated circuit comprises a transmitter, a path coupled to the transmitter, and a TDR receiver integrated with the transmitter for analyzing a reflected signal from the path. The TDR receiver compares the reflected signal with a variable reference signal to generate a logic state at a sampling instant determined by a timebase generated by a sampling circuit. The reflected signal equals the variable reference signal when the logic state transitions. The reference signal and the corresponding timebase value are recorded at the logic state transition. A waveform is generated from the recorded reference signal and its corresponding timebase value. A reference point for the waveform is determined. The location of a fault on the transmission line can be determined from the timebase value difference between the reference point and the fault.

Abstract: A system that restricts the damaging effects of software faults that interact with test and configuration circuitry. This test and configuration circuitry includes a scan chain in the form of a serial linkage between memory elements within a circuit, thereby allowing a test input to be serially shifted into the memory elements. The system operates by receiving a test disable signal at the circuit. In response to the test disable signal, the system moves the circuit into a test disable mode, which limits any damaging effects to the circuit caused by shifting the test input into the memory elements in the scan chain. Next, the system shifts the test input into the memory elements in the scan chain. T he system also determines whether the test input will cause damage to the circuit after the test input is completely shifted into the scan chain. If so, the system holds the circuit in the test disable mode so that the test input cannot damage the circuit.

Abstract: A fault-tolerant computer architecture is described wherein the effect of hardware faults is diminished. The architecture employs a main data bus having a plurality of interface slots for interconnecting conventional computer sub-systems. The number and type of sub-systems may vary considerably, however, a central processor sub-system which encompasses the inventive elements of the invention is always included. The central processor sub-system employs a plurality of central processing modules operating in parallel in a substantially synchronized manner. One of the central processing modules operates as a master central processing module, and is the only module capable of reading data from and writing data to the main data bus. The master central processing module is initially chosen arbitrarily from among the central processing modules.

Abstract: A system for limiting security attacks on a computer system that operate by executing computer instructions embedded in data received from an external source. The system receives the data from the external source and performs a transformation on the data that causes any computer instructions encoded in the data to be unexecutable. After the data is transformed, the system stores the data in the computer system's memory. When the data is needed, the system retrieves the data and reverses the transformation. In this way, data from an external source is stored in memory in an unexecutable form, thereby making it impossible to execute malicious code embedded in the data. According to one aspect of the present invention, the data is transformed using a random number, so that the data can only be converted back to its original form with an inverse transformation using the same random number.

Abstract: A system and method for providing redundant, synchronized clocks in a computer system. Upon a failure of a master clock signal, the system switches over to a slave clock signal synchronized with the master clock signal. Switching logic is coupled to receive a first clock signal and a second clock signal. The switching logic selects either the first clock signal or the second clock signal as a local clock signal. The switching logic further monitors the first clock signal for a failure. If a failure is monitored, the switching logic accepts the second clock signal as the local clock signal in place of the first clock signal. One or more clock local loads operate according to the local clock signal. The switching logic may control the input to a phase locked loop (PLL) that provides the local clock signal to the local clock loads. The method includes a PLL synchronizing an output clock signal with the master clock signal. The output clock signal is used by at least one local clock load for timing.

Abstract: A program controlled apparatus includes one or more units for executing a multiple process. A mutex ordering mechanism controls the ordering of mutex ownership to provide deterministic execution of the processes. A mutex processor monitors mutex registers for determining mutex ownership. The mutex registers can be configured as sets of mutex request registers and mutex release registers. The apparatus may include a single processor configured to execute multiple processes concurrently, or multiple processing units, each configured to execute one or more processes. A monitor unit which can monitor equivalent operation of the processing sets can also include the mutex ordering mechanism.