Patents by Inventor Emrys J. Williams

Emrys J. Williams has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System and method for reducing the effects of hardware faults in a computer system employing multiple central processing modules
    Patent number: 5889940
    Abstract: A fault-tolerant computer architecture is described wherein the effect of hardware faults is diminished. The architecture employs a main data bus having a plurality of interface slots for interconnecting conventional computer sub-systems. The number and type of sub-systems may vary considerably, however, a central processor sub-system which encompasses the inventive elements of the invention is always included. The central processor sub-system employs a plurality of central processing modules operating in parallel in a substantially synchronized manner. One of the central processing modules operates as a master central processing module, and is the only module capable of reading data from and writing data to the main data bus. The master central processing module is initially chosen arbitrarily from among the central processing modules.
    Type: Grant
    Filed: January 25, 1997
    Date of Patent: March 30, 1999
    Assignee: Sun Microsystems, Inc.
    Inventors: David C. Liddell, Emrys J. Williams
  • Method and apparatus for reducing the effects of hardware faults in a computer system employing multiple central processing modules
    Patent number: 5627965
    Abstract: A fault-tolerant computer architecture is described wherein the effect of hardware faults is diminished. The architecture employs a main data bus having a plurality of interface slots for interconnecting conventional computer sub-systems. The number and type of sub-systems may vary considerably, however, a central processor sub-system which encompasses the inventive elements of the invention is always included. The central processor sub-system employs a plurality of central processing modules operating in parallel in a substantially synchronized manner. One of the central processing modules operates as a master central processing module, and is the only module capable of reading data from and writing data to the main data bus. The master central processing module is initially chosen arbitrarily from among the central processing modules.
    Type: Grant
    Filed: October 27, 1994
    Date of Patent: May 6, 1997
    Assignee: Integrated Micro Products, Ltd.
    Inventors: David C. Liddell, Emrys J. Williams