Patents by Inventor En-Chiuan Liou

En-Chiuan Liou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10879378
    Abstract: Provided is a semiconductor structure including a substrate, a doping layer, and a dielectric layer. The substrate has a plurality of fin portions and at least one recessed portion, wherein the at least one recessed portion is located between two adjacent fin portions of the plurality of fin portions and a bottom surface of the at least one recessed portion is lower than a surface of the substrate between the two of the plurality of fin portions. The doping layer is disposed on a sidewall of the plurality of fin portions, the surface of the substrate, and a sidewall and a bottom portion of the at least one recessed portion. The dielectric layer is disposed on the doping layer. A top surface of the doping layer and a top surface of the dielectric layer are lower than a top surface of each of the plurality of fin portions.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: December 29, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Yu-Cheng Tung
  • Patent number: 10861673
    Abstract: A method of pattern data preparation includes the following steps. A desired pattern to be formed on a surface of a layer is inputted. A first set of beam shots are determined, and a first calculated pattern on the surface is calculated from the first set of beam shots. The first calculated pattern is rotated, so that a boundary of the desired pattern corresponding to a non-smooth boundary of the first calculated pattern is parallel to a boundary constituted by beam shots. A second set of beam shots are determined to revise the non-smooth boundary of the first calculated pattern, thereby calculating a second calculated pattern being close to the desired pattern on the surface. The present invention also provides a method of forming a pattern in a layer.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: December 8, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Ying Sun, En-Chiuan Liou, Yu-Cheng Tung
  • Patent number: 10818660
    Abstract: A manufacturing method of a semiconductor device includes the following steps. A semiconductor substrate including at least one fin structure is provided. A gate material layer is formed on the semiconductor substrate, and the fin structure is covered by the gate material layer. A trench is formed partly in the gate material layer and partly in the fin structure. An isolation structure is formed partly in the trench and partly outside the trench. At least one gate structure is formed straddling the fin structure by patterning the gate material layer after the step of forming the isolation structure. A top surface of the isolation structure is higher than a top surface of the gate structure in a vertical direction for enhancing the isolation performance of the isolation structure. A sidewall spacer is formed on sidewalls of the isolation structure, and there is no gate structure formed on the isolation structure.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: October 27, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Yu-Cheng Tung, Chih-Wei Yang
  • Patent number: 10790202
    Abstract: The present invention provides an overlay mark, including a substrate and plural sets of first pattern block and second pattern block. A first direction and a second direction are defined on the substrate, wherein the first direction and the second direction are perpendicular to each other. In each set, the first pattern block is rotational symmetrical to the second pattern block. Each first pattern block includes a big frame and plural small frame. Each second pattern block includes a big frame and plural small frame. The width of the big frame is greater than three times of the width of the small frame. The present invention further provides a method for evaluating the stability of a semiconductor manufacturing process.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: September 29, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Yu-Cheng Tung
  • Patent number: 10777556
    Abstract: A semiconductor device includes a semiconductor substrate, semiconductor fins; and a first fin bump between the semiconductor fins. The first fin bump includes a first sidewall spacer. The first sidewall spacer includes a solid-state dopant source layer and an insulating buffer layer.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: September 15, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Yu-Cheng Tung
  • Patent number: 10763264
    Abstract: The present invention provides a method for forming a dynamic random access memory (DRAM) structure, the method including: firstly, a substrate is provided, a cell region and a peripheral region are defined on the substrate, a plurality of buried word lines is then formed in the cell region of the substrate, next, a shallow trench isolation structure is formed in the peripheral region adjacent to the cell region, wherein a concave top surface is formed on the shallow trench isolation structure, afterwards, a first dummy bit line gate is formed within the shallow trench isolation structure of the peripheral area, and a second dummy bit line gate is formed in the cell region and adjacent to the first dummy bit line gate, wherein a top surface of the first dummy bit line gate is lower than a top surface of the second dummy bit line gate.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: September 1, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: En-Chiuan Liou, Yu-Cheng Tung, Chih-Wei Yang, Sho-Shen Lee
  • Patent number: 10763175
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a plurality of fin shaped structures and an insulating layer. The substrate has a fin field-effect transistor (finFET) region, a first region, a second region and a third region. The first region, the second region and the third region have a first surface, a second surface, and a third surface, respectively, where the first surface is relatively higher than the second surface and the second surface is relatively higher than the third surface. The fin shaped structures are disposed on a surface of the fin field-effect transistor region. The insulating layer covers the first surface, the second surface and the third surface.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: September 1, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Yu-Cheng Tung
  • Patent number: 10707213
    Abstract: A method of forming a layout of a semiconductor device includes the following steps. First line patterns extend along a first direction in a first area and a second area, but the first line patterns extend along a second direction in a boundary area. Second line patterns extend along a third direction in the first area and the second area, but the second line patterns extend along a fourth direction in the boundary area, so that minimum distances between overlapping areas of the first line patterns and the second line patterns in the boundary area are larger than minimum distances between overlapping areas of the first line patterns and the second line patterns in the first area and the second area. A trimming process is performed to shade the first line patterns and the second line patterns in the boundary area and the second area.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: July 7, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chia-Hung Wang, En-Chiuan Liou, Chien-Hao Chen, Sho-Shen Lee, Yi-Ting Chen, Jhao-Hao Lee
  • Patent number: 10707092
    Abstract: The present invention provides a method of fabricating a semiconductor pattern. Firstly, a substrate is provided, having an oxide layer thereon and a first material layer on the oxide layer, a first region and a second region are defined on the substrate. A first etching step is performed, to remove a portion of the first material layer in the first region, and then a plurality of first patterns are formed on the first material layer in the first region. A second composite layer is formed on the first pattern. Next, a second pattern layer is formed on the second composite layer in the first region, and a second etching step is performed, using the first pattern and the second pattern as a mask, to remove a portion of the second composite layer, a portion of the first material layer and a portion of the oxide layer.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: July 7, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Hung Wang, En-Chiuan Liou, Chien-Hao Chen, Jhao-Hao Lee, Sho-Shen Lee, Chih-Yu Chiang
  • Publication number: 20200203176
    Abstract: The present invention provides a method of fabricating a semiconductor pattern. Firstly, a substrate is provided, having an oxide layer thereon and a first material layer on the oxide layer, a first region and a second region are defined on the substrate. A first etching step is performed, to remove a portion of the first material layer in the first region, and then a plurality of first patterns are formed on the first material layer in the first region. A second composite layer is formed on the first pattern. Next, a second pattern layer is formed on the second composite layer in the first region, and a second etching step is performed, using the first pattern and the second pattern as a mask, to remove a portion of the second composite layer, a portion of the first material layer and a portion of the oxide layer.
    Type: Application
    Filed: January 10, 2019
    Publication date: June 25, 2020
    Inventors: Chia-Hung Wang, En-Chiuan Liou, Chien-Hao Chen, Jhao-Hao Lee, Sho-Shen Lee, Chih-Yu Chiang
  • Publication number: 20200185511
    Abstract: Provided is a semiconductor structure including a substrate, a doping layer, and a dielectric layer. The substrate has a plurality of fin portions and at least one recessed portion, wherein the at least one recessed portion is located between two adjacent fin portions of the plurality of fin portions and a bottom surface of the at least one recessed portion is lower than a surface of the substrate between the two of the plurality of fin portions. The doping layer is disposed on a sidewall of the plurality of fin portions, the surface of the substrate, and a sidewall and a bottom portion of the at least one recessed portion. The dielectric layer is disposed on the doping layer. A top surface of the doping layer and a top surface of the dielectric layer are lower than a top surface of each of the plurality of fin portions.
    Type: Application
    Filed: February 14, 2020
    Publication date: June 11, 2020
    Applicant: United Microelectronics Corp.
    Inventors: EN-CHIUAN LIOU, Yu-Cheng Tung
  • Patent number: 10663853
    Abstract: An extreme ultraviolet (EUV) mask includes: a substrate having a first region and a second region; a reflective layer on the substrate; an absorbing layer on the reflective layer; and a first recess in the absorbing layer and in part of the reflective layer on the first region. Preferably, a bottom surface of the first recess exposes a top surface of the reflective layer.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: May 26, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Yu-Cheng Tung
  • Publication number: 20200111791
    Abstract: A method of forming a layout of a semiconductor device includes the following steps. First line patterns extend along a first direction in a first area and a second area, but the first line patterns extend along a second direction in a boundary area. Second line patterns extend along a third direction in the first area and the second area, but the second line patterns extend along a fourth direction in the boundary area, so that minimum distances between overlapping areas of the first line patterns and the second line patterns in the boundary area are larger than minimum distances between overlapping areas of the first line patterns and the second line patterns in the first area and the second area. A trimming process is performed to shade the first line patterns and the second line patterns in the boundary area and the second area.
    Type: Application
    Filed: November 1, 2018
    Publication date: April 9, 2020
    Inventors: Chia-Hung Wang, En-Chiuan Liou, Chien-Hao Chen, Sho-Shen Lee, Yi-Ting Chen, Jhao-Hao Lee
  • Patent number: 10600692
    Abstract: A semiconductor device includes a substrate having a fin structure extending along a first direction. The fin structure protrudes from a top surface of a trench isolation region and has a first height. A plurality of gate lines including a first gate line and a second gate line extend along a second direction and striding across the fin structure. The first gate line has a discontinuity directly above a gate cut region. The second gate line is disposed in proximity to a dummy fin region, and does not overlap with the dummy fin region. The fin structure has a second height within the dummy fin region, and the second height is smaller than the first height.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: March 24, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hsiao-Lin Hsu, En-Chiuan Liou
  • Publication number: 20200083020
    Abstract: A method of pattern data preparation includes the following steps. A desired pattern to be formed on a surface of a layer is inputted. A first set of beam shots are determined, and a first calculated pattern on the surface is calculated from the first set of beam shots. The first calculated pattern is rotated, so that a boundary of the desired pattern corresponding to a non-smooth boundary of the first calculated pattern is parallel to a boundary constituted by beam shots. A second set of beam shots are determined to revise the non-smooth boundary of the first calculated pattern, thereby calculating a second calculated pattern being close to the desired pattern on the surface. The present invention also provides a method of forming a pattern in a layer.
    Type: Application
    Filed: September 26, 2018
    Publication date: March 12, 2020
    Inventors: Chien-Ying Sun, En-Chiuan Liou, Yu-Cheng Tung
  • Patent number: 10571796
    Abstract: An extreme ultraviolet (EUV) photomask includes a mask substrate, a reflection layer and a light-absorbing pattern layer. The reflection layer is disposed on the mask substrate, wherein the reflection layer has a concave pattern. The light-absorbing pattern layer is in the reflection layer, to fill the concave pattern. The light-absorbing pattern layer is exposed.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: February 25, 2020
    Assignee: United Microelectronics Corp.
    Inventors: En-Chiuan Liou, Yu-Cheng Tung
  • Publication number: 20200035782
    Abstract: The present invention provides a semiconductor structure including a substrate including a plurality of capacitor lower electrodes, the capacitor lower electrodes are arranged in a diamond array along a first direction and a second direction respectively, the first direction and the second direction are not perpendicular to each other. A supporting structure layer contacts at least parts of the capacitor lower electrodes, wherein the supporting structure layer includes a plurality of triangular openings, and the three corners of each triangular opening are overlapped with three adjacent capacitor lower electrodes respectively.
    Type: Application
    Filed: August 29, 2018
    Publication date: January 30, 2020
    Inventors: Li-Wei Feng, En-Chiuan Liou, Yu-Cheng Tung, Wei-Lun Hsu, Yu-Hsiang Hung, Ming-Te Wei, Le-Tien Jung
  • Publication number: 20200013783
    Abstract: The present invention provides a method for forming a dynamic random access memory (DRAM) structure, the method including: firstly, a substrate is provided, a cell region and a peripheral region are defined on the substrate, a plurality of buried word lines is then formed in the cell region of the substrate, next, a shallow trench isolation structure is formed in the peripheral region adjacent to the cell region, wherein a concave top surface is formed on the shallow trench isolation structure, afterwards, a first dummy bit line gate is formed within the shallow trench isolation structure of the peripheral area, and a second dummy bit line gate is formed in the cell region and adjacent to the first dummy bit line gate, wherein a top surface of the first dummy bit line gate is lower than a top surface of the second dummy bit line gate.
    Type: Application
    Filed: September 16, 2019
    Publication date: January 9, 2020
    Inventors: En-Chiuan Liou, Yu-Cheng Tung, Chih-Wei Yang, Sho-Shen Lee
  • Publication number: 20200013724
    Abstract: A method of forming an overlay mark structure includes the following steps. An insulation layer is formed on a substrate. A first overlay mark is formed in the insulation layer. A metal layer is formed on the substrate. The metal layer covers the insulation layer and the first overlay mark. The metal layer on the first overlay mark is removed. A top surface of the first overlay mark is lower than a top surface of the insulation layer after the step of removing the metal layer on the first overlay mark. A second overlay mark is formed on the metal layer. In the method of forming the overlay mark structure, the first overlay mark may not be covered by the metal layer for avoiding influences on related measurements, and the second overlay mark may be formed on the metal layer for avoiding related defects generated by the height difference.
    Type: Application
    Filed: July 31, 2018
    Publication date: January 9, 2020
    Inventors: Zheng-Feng Chen, Sho-Shen Lee, En-Chiuan Liou, Hsiao-Lin Hsu, Yi-Ting Chen, Lu-Wei Kuo
  • Patent number: 10529667
    Abstract: A method of forming an overlay mark structure includes the following steps. An insulation layer is formed on a substrate. A first overlay mark is formed in the insulation layer. A metal layer is formed on the substrate. The metal layer covers the insulation layer and the first overlay mark. The metal layer on the first overlay mark is removed. A top surface of the first overlay mark is lower than a top surface of the insulation layer after the step of removing the metal layer on the first overlay mark. A second overlay mark is formed on the metal layer. In the method of forming the overlay mark structure, the first overlay mark may not be covered by the metal layer for avoiding influences on related measurements, and the second overlay mark may be formed on the metal layer for avoiding related defects generated by the height difference.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: January 7, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Zheng-Feng Chen, Sho-Shen Lee, En-Chiuan Liou, Hsiao-Lin Hsu, Yi-Ting Chen, Lu-Wei Kuo