Patents by Inventor En-Chiuan Liou

En-Chiuan Liou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10043807
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a plural fin structures, two gates, a protection layer and an interlayer dielectric layer. The fin structures are disposed on a substrate. The two gates are disposed on the substrate across the fin structures. The protection layer is disposed on the substrate, surrounded sidewalls of the two gates. The interlayer dielectric layer is disposed on the substrate, covering the fin structures and the two gates.
    Type: Grant
    Filed: July 4, 2017
    Date of Patent: August 7, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Rung-Yuan Lee, Yu-Cheng Tung, Chun-Tsen Lu, En-Chiuan Liou, Kuan-Hung Chen
  • Publication number: 20180218917
    Abstract: A method of patterning a semiconductor device includes following steps. First of all, a substrate is provided, and a first target pattern is formed in the substrate. Next, a second target pattern is formed on the substrate, across the first target pattern. Then, a third pattern is formed on a hard mask layer formed on the substrate, by using an electron beam apparatus, wherein two opposite edges of the third pattern are formed under an asymmetry control.
    Type: Application
    Filed: February 2, 2017
    Publication date: August 2, 2018
    Inventors: En-Chiuan Liou, Hon-Huei Liu, Chia-Hung Lin, Yu-Cheng Tung
  • Publication number: 20180203344
    Abstract: A photomask includes a substrate, a patterned absorber layer disposed on the substrate, and a plurality of openings. Each of the openings penetrates the patterned absorber layer and exposes a part of the substrate. At least two of the openings are disposed adjacent to each other in a first direction. At least a part of the patterned absorber layer disposed between the two adjacent openings in the first direction has a first thickness. A part of the patterned absorber layer disposed at two opposite edges of each of the openings in a second direction different from the first direction has a second thickness. Another part of the patterned absorber layer disposed at the two opposite edges of each of the openings in the second direction has a third thickness. The first thickness is equal to the second thickness, and the first thickness is different from the third thickness.
    Type: Application
    Filed: February 18, 2017
    Publication date: July 19, 2018
    Inventors: En-Chiuan Liou, Yu-Cheng Tung, Chia-Hung Lin
  • Patent number: 10019884
    Abstract: A safety care system is for use with a supporting device that is provided with a surface for a person to lie thereon. The safety care system includes a safety control device. The safety control device includes a breathable lining and a control module. The breathable lining is used to cover the surface for the person to lie thereon. The control module receives a signal that is associated with the person, and separates the breathable lining and the surface in response to receipt of the signal.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: July 10, 2018
    Inventor: En-Chiuan Liou
  • Patent number: 9991337
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region and a second region; forming a plurality of fin-shaped structures and a first shallow trench isolation (STI) around the fin-shaped structures on the first region and the second region; forming a patterned hard mask on the second region; removing the fin-shaped structures and the first STI from the first region; forming a second STI on the first region; removing the patterned hard mask; and forming a gate structure on the second STI.
    Type: Grant
    Filed: August 30, 2015
    Date of Patent: June 5, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Chih-Wei Yang, Yu-Cheng Tung, Chun-Yuan Wu
  • Publication number: 20180151371
    Abstract: A semiconductor device includes first fin-shaped structures and second fin-shaped structures, which are separately disposed on a semiconductor substrate. Each of the first and second fin-shaped structures includes a base portion and a top portion protruding from the top portion. The base portions of the second fin-shaped structures are wider than the top portions of the second fin-shaped structures, and the top portions of the second fin-shaped structures are as wide as the top portions of the first fin-shaped structures. Each second fin-shaped structure further includes a recessed region on its sidewall.
    Type: Application
    Filed: January 25, 2018
    Publication date: May 31, 2018
    Inventors: En-Chiuan Liou, Yu-Cheng Tung
  • Publication number: 20180149978
    Abstract: A method for forming a patterned structure includes following steps. First lines elongated in a first direction and second lines elongated in a second direction in a layout pattern are decomposed into two masks. A first mask includes first line patterns and a first block pattern. A second mask includes second line patterns and a second block pattern. Two photolithography processes with the first mask and the second mask are performed for forming a patterned structure including first line structures and second line structures. Each first line structure is elongated in the first direction. The first line structures are defined by a region where the first line patterns and the second block pattern overlap with one another. Each second line structure is elongated in the second direction. The second line structures are defined by a region where the second line patterns and the first block pattern overlap with one another.
    Type: Application
    Filed: November 25, 2016
    Publication date: May 31, 2018
    Inventors: En-Chiuan Liou, Yu-Cheng Tung
  • Publication number: 20180140492
    Abstract: A health-care device for supporting a human body rested on a carrier includes an air-permeable member, a moving unit, an air regulating unit and a control unit. The air-permeable member is connected with the carrier and under the human body. A moving unit is operative to move the carrier or the air-permeable member to generate an airflow space between the carrier and the human body. An air regulating unit is operative to permit air flowing through the airflow space to reduce the discomfort feeling of the bedridden patient. The control unit is connected to control the air regulating unit and the moving unit.
    Type: Application
    Filed: November 22, 2017
    Publication date: May 24, 2018
    Inventor: En-Chiuan LIOU
  • Publication number: 20180144988
    Abstract: A semiconductor device includes a semiconductor substrate, a shallow trench isolation structure, gate electrodes, and a gate isolation structure. The semiconductor substrate includes fin structures, and each of the fin structures is elongated in a first direction. The shallow trench isolation structure is disposed on the semiconductor substrate and disposed between the fin structures. The gate electrodes are disposed on the semiconductor substrate and the shallow trench isolation structure. Each of the gate electrodes is elongated in a second direction and disposed straddling at least one of the fin structures. The gate isolation structure is disposed between two adjacent gate electrodes in the second direction, and a bottom surface of the gate isolation structure is lower than a top surface of the shallow trench isolation structure. The gate isolation structure is aligned with the gate electrodes adjacent to the gate isolation structure in the second direction.
    Type: Application
    Filed: January 4, 2018
    Publication date: May 24, 2018
    Inventors: En-Chiuan Liou, Yu-Cheng Tung
  • Patent number: 9978873
    Abstract: The present invention provides a method of fabricating a FinFET, comprising the following steps: first, a substrate having a plurality of fin structures disposed thereon is provided, an STI disposed between adjacent fin structures and a gate structure crossing the fin structures. Next, the fin structures not covered by the gate structure and the STI not covered by the gate structure are etched, until the STI is removed entirely and a first recessed and protruding profile is formed on the substrate, wherein the first recessed and protruding profile includes a first recess and a plurality of second recesses, and the position of the second recesses corresponds to the position of the fin structures, and an epitaxial layer is formed on the first recessed and protruding profile.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: May 22, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Yu-Cheng Tung
  • Publication number: 20180138180
    Abstract: A semiconductor device includes a semiconductor substrate having a first region and a second region, a plurality of first semiconductor fins in the first region, a plurality of second semiconductor fins in the second region, a first solid-state dopant source layer within the first region on the semiconductor substrate, a first insulating buffer layer on the first solid-state dopant source layer, a second solid-state dopant source layer within the second region on the semiconductor substrate, a second insulating buffer layer on the second solid-state dopant source layer and on the first insulating buffer layer, a first fin bump in the first region, and a second fin bump in the second region. The first fin bump includes a first sidewall spacer and the second fin bump comprises a second sidewall spacer. The first sidewall spacer has a structure that is different from that of the second sidewall spacer.
    Type: Application
    Filed: November 3, 2017
    Publication date: May 17, 2018
    Inventors: En-Chiuan Liou, Yu-Cheng Tung
  • Patent number: 9964866
    Abstract: A method of forming an integrated circuit includes the following steps. A substrate including a plurality of exposure fields is provided, and each of the exposure field includes a target portion and a set of alignment marks. Measure the set of alignment marks of each exposure field by a measuring system to obtain alignment data for the respective exposure field. Determine an exposure parameter corresponding to each exposure field and an exposure location on the target portion from the alignment data for the respective exposure field by a calculating system. Feedback the alignment data to a next substrate.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: May 8, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Che-Yi Lin, En-Chiuan Liou, Chia-Hsun Tseng, Yi-Ting Chen, Chia-Hung Wang, Yi-Jing Wang
  • Publication number: 20180097109
    Abstract: The present invention provides a semiconductor device, including a substrate, two gate structures disposed on a channel region of the substrate, an epitaxial layer disposed in the substrate between two gate structures, a first dislocation disposed in the epitaxial layer, wherein the profile of the first dislocation has at least two non-parallel slanting lines, and a second dislocation disposed adjacent to a top surface of the epitaxial layer, and the profile of the second dislocation has at least two non-parallel slanting lines.
    Type: Application
    Filed: December 5, 2017
    Publication date: April 5, 2018
    Inventors: En-Chiuan Liou, Yu-Cheng Tung
  • Publication number: 20180097098
    Abstract: The present invention provides a method of fabricating a FinFET, comprising the following steps: first, a substrate having a plurality of fin structures disposed thereon is provided, an STI disposed between adjacent fin structures and a gate structure crossing the fin structures. Next, the fin structures not covered by the gate structure and the STI not covered by the gate structure are etched, until the STI is removed entirely and a first recessed and protruding profile is formed on the substrate, wherein the first recessed and protruding profile includes a first recess and a plurality of second recesses, and the position of the second recesses corresponds to the position of the fin structures, and an epitaxial layer is formed on the first recessed and protruding profile.
    Type: Application
    Filed: December 7, 2017
    Publication date: April 5, 2018
    Inventors: En-Chiuan Liou, Yu-Cheng Tung
  • Patent number: 9922834
    Abstract: A semiconductor device includes first fin-shaped structures and second fin-shaped structures, which are separately disposed on a semiconductor substrate. Each of the first and second fin-shaped structures includes a base portion and a top portion protruding from the top portion. The base portions of the second fin-shaped structures are wider than the top portions of the second fin-shaped structures, and the top portions of the second fin-shaped structures are as wide as the top portions of the first fin-shaped structures. Each second fin-shaped structure further includes a recessed region on its sidewall.
    Type: Grant
    Filed: August 7, 2015
    Date of Patent: March 20, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Yu-Cheng Tung
  • Publication number: 20180061963
    Abstract: A fabricating method of a semiconductor structure includes the following steps. A gate material layer is formed on a semiconductor substrate. A patterned mask layer is formed on the gate material layer. The pattern mask layer includes at least one opening exposing a part of the gate material layer. An impurity treatment is performed to the gate material layer partially covered by the pattern mask layer for forming at least one doped region in the gate material layer. An etching process is performed to remove the gate material layer including the doped region. A dummy gate may be formed by patterning the gate material layer, and the impurity treatment may be performed after the step of forming the dummy gate. The performance of the etching processes for removing the gate material layer and/or the dummy gate may be enhanced, and the gate material residue issue may be solved accordingly.
    Type: Application
    Filed: August 30, 2016
    Publication date: March 1, 2018
    Inventors: Wen-Chien Hsieh, En-Chiuan Liou, Chih-Wei Yang, Yu-Cheng Tung, Po-Wen Su
  • Publication number: 20180053761
    Abstract: A manufacturing method of a semiconductor device includes the following steps. A semiconductor substrate including at least one fin structure is provided. A gate material layer is formed on the semiconductor substrate, and the fin structure is covered by the gate material layer. A trench is formed partly in the gate material layer and partly in the fin structure. An isolation structure is formed partly in the trench and partly outside the trench. At least one gate structure is formed straddling the fin structure by patterning the gate material layer after the step of forming the isolation structure. A top surface of the isolation structure is higher than a top surface of the gate structure in a vertical direction for enhancing the isolation performance of the isolation structure. A sidewall spacer is formed on sidewalls of the isolation structure, and there is no gate structure formed on the isolation structure.
    Type: Application
    Filed: August 21, 2016
    Publication date: February 22, 2018
    Inventors: En-Chiuan Liou, Yu-Cheng Tung, Chih-Wei Yang
  • Patent number: 9899267
    Abstract: A semiconductor device includes a semiconductor substrate, a shallow trench isolation structure, a plurality of gate electrodes, and a gate isolation structure. The semiconductor substrate includes a plurality of fin structures, and each of the fin structures is elongated in a first direction. The shallow trench isolation structure is disposed on the semiconductor substrate and disposed between the fin structures. The gate electrodes are disposed on the semiconductor substrate and the shallow trench isolation structure. Each of the gate electrodes is elongated in a second direction and disposed straddling at least one of the fin structures. The gate isolation structure is disposed between two adjacent gate electrodes in the second direction, and a bottom surface of the gate isolation structure is lower than a top surface of the shallow trench isolation structure.
    Type: Grant
    Filed: December 25, 2016
    Date of Patent: February 20, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Yu-Cheng Tung
  • Publication number: 20180047635
    Abstract: A semiconductor device includes a semiconductor substrate, an isolation structure, and a spacer. The semiconductor substrate includes at least one fin structure. The isolation structure is partly disposed in the fin structure and partly disposed above the fin structure. The fin structure includes a first fin and a second fin elongated in the same direction. A part of the isolation structure is disposed between the first fin and the second fin in the direction where the first fin and the second fin are elongated. The spacer is disposed on sidewalls of the isolation structure on the fin structure. The isolation structure in the present invention is partly disposed in the fin structure and partly disposed above the fin structure. The negative influence of a gate structure formed on the isolation structure and sinking into the isolation structure on the isolation performance of the isolation structure may be avoided accordingly.
    Type: Application
    Filed: September 13, 2016
    Publication date: February 15, 2018
    Inventors: En-Chiuan Liou, Yu-Cheng Tung, Chih-Wei Yang
  • Publication number: 20180047848
    Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device includes a plurality of fin shaped structures, a trench, a spacing layer and a dummy gate structure. The fin shaped structures are disposed on a substrate. The trench is disposed between the fin shaped structures. The spacing layer is disposed on sidewalls of the trench, wherein the spacing layer has a top surface lower than a top surface of the fin shaped structures. The dummy gate structure is disposed on the fin shaped structures and across the trench.
    Type: Application
    Filed: October 30, 2017
    Publication date: February 15, 2018
    Inventors: En-Chiuan Liou, Tang-Chun Weng, Chien-Hao Chen