Patents by Inventor En-Chiuan Liou

En-Chiuan Liou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180040693
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a plurality of fin-shaped structures and a first shallow trench isolation (STI) around the fin-shaped structures on the first region and the second region; forming a patterned hard mask on the second region; removing the fin-shaped structures and the first STI from the first region; forming a second STI on the first region; removing the patterned hard mask; and forming a gate structure on the second STI.
    Type: Application
    Filed: October 18, 2017
    Publication date: February 8, 2018
    Inventors: En-Chiuan Liou, Chih-Wei Yang, Yu-Cheng Tung, Chun-Yuan Wu
  • Patent number: 9882054
    Abstract: A FinFET is provided. The FinFET includes a substrate. A plurality of fin structures are defined on the substrate. A gate structure crosses each fin structure. Two first recesses are disposed on two sides of the gate structure respectively, wherein each first recess further includes a plurality of second recesses disposed therein, and the position of each second recess corresponds to each fin structure. Two epitaxial layers are disposed at two sides of the gate structure respectively and in the first recesses, each epitaxial layer has a bottom surface including a second concave and convex profile, and each epitaxial layer directly contacts a bottom surface of each first recess and a bottom surface of each second recess.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: January 30, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Yu-Cheng Tung
  • Patent number: 9875928
    Abstract: A method for fabricating metal interconnect structure is disclosed. The method includes the steps of: providing a substrate having a first inter-metal dielectric (IMD) layer thereon; forming a metal interconnection in the first IMD layer; removing part of the first IMD layer; forming a spacer adjacent to the metal interconnection; and using the spacer as mask to remove part of the first IMD layer for forming an opening in the first IMD layer.
    Type: Grant
    Filed: April 9, 2015
    Date of Patent: January 23, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Yu-Cheng Tung, Chih-Wei Yang
  • Patent number: 9875937
    Abstract: The present invention provides a method for forming a semiconductor structure. Firstly, a substrate is provided, the substrate comprises an insulating layer and at least one first nano channel structure disposed thereon, a first region and a second region being defined on the substrate, next, a hard mask is formed within the first region, afterwards, an etching process is performed, to remove parts of the insulating layer within the second region, an epitaxial process is then performed, to form an epitaxial layer on the first nano channel structure, and an anneal process is performed, to transform the first nano channel structure and the epitaxial layer into a first nanowire structure, wherein the diameter of the first nanowire structure within the first region is different from the diameter of the first nanowire structure within the second region.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: January 23, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Yu-Cheng Tung, Chih-Wei Yang
  • Patent number: 9871001
    Abstract: A method of manufacturing an integrated circuit includes the following steps. A substrate including a plurality of exposure fields is provided, and each of the exposure fields includes a target portion and a set of overlay marks. The substrate is exposed to form a first layer lithography pattern on the target portion for the respective exposure field by an exposure system. The overlay of the first layer lithography pattern and the target portion is measured by the set of overlay marks of each exposure field to obtain first overlay data for the respective exposure field by a measuring system. The first overlay data is fed to form a second layer lithography pattern.
    Type: Grant
    Filed: May 3, 2016
    Date of Patent: January 16, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: En-Chiuan Liou
  • Patent number: 9871138
    Abstract: The present invention provides a semiconductor device, including a substrate, two gate structures disposed on a channel region of the substrate, an epitaxial layer disposed in the substrate between two gate structures, a first dislocation disposed in the epitaxial layer, wherein the profile of the first dislocation has at least two non-parallel slanting lines, and a second dislocation disposed adjacent to a top surface of the epitaxial layer, and the profile of the second dislocation has at least two non-parallel slanting lines.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: January 16, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Yu-Cheng Tung
  • Patent number: 9837417
    Abstract: A semiconductor device includes a semiconductor substrate having a first region and a second region, a plurality of first semiconductor fins in the first region, a plurality of second semiconductor fins in the second region, a first solid-state dopant source layer within the first region on the semiconductor substrate, a first insulating buffer layer on the first solid-state dopant source layer, a second solid-state dopant source layer within the second region on the semiconductor substrate, a second insulating buffer layer on the second solid-state dopant source layer and on the first insulating buffer layer, a first fin bump in the first region, and a second fin bump in the second region. The first fin bump includes a first sidewall spacer and the second fin bump comprises a second sidewall spacer. The first sidewall spacer has a structure that is different from that of the second sidewall spacer.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: December 5, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Yu-Cheng Tung
  • Patent number: 9837282
    Abstract: A semiconductor structure includes a semiconductor substrate with a first region and a second region defined thereon. The first region is disposed adjoining the second region in a first direction. The semiconductor substrate includes fin structures, first recessed fins, and a bump. The fin structures are disposed in the first region. Each fin structure is elongated in the first direction. The first recessed fins are disposed in the second region. Each first recessed fin is elongated in the first direction. A topmost surface of each first recessed fin is lower than a topmost surface of each fin structure. The bump is disposed in the second region and disposed between two adjacent recessed fins in the first direction. A topmost surface of the bump is higher than the topmost surface of each first recessed fin and lower than the topmost surface of each fin structure.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: December 5, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tang-Chun Weng, Chia-Ching Lin, Yen-Pu Chen, En-Chiuan Liou
  • Patent number: 9837540
    Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device includes a plurality of fin shaped structures, a trench, a spacing layer and a dummy gate structure. The fin shaped structures are disposed on a substrate. The trench is disposed between the fin shaped structures. The spacing layer is disposed on sidewalls of the trench, wherein the spacing layer has a top surface lower than a top surface of the fin shaped structures. The dummy gate structure is disposed on the fin shaped structures and across the trench.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: December 5, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Tang-Chun Weng, Chien-Hao Chen
  • Patent number: 9837511
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having at least a fin-shaped structure thereon and the fin-shaped structure includes a top portion and a bottom portion; forming a gate structure on the fin-shaped structure; forming a cap layer on the top portion of the fin-shaped structure not covered by the gate structure; performing an annealing process to drive germanium from the cap layer to the top portion of the fin-shaped structure; removing the cap layer; and forming an epitaxial layer around the top portion of the fin-shaped structure.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: December 5, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Cheng Tung, En-Chiuan Liou
  • Publication number: 20170323854
    Abstract: A method of manufacturing an integrated circuit includes the following steps. A substrate including a plurality of exposure fields is provided, and each of the exposure fields includes a target portion and a set of overlay marks. The substrate is exposed to form a first layer lithography pattern on the target portion for the respective exposure field by an exposure system. The overlay of the first layer lithography pattern and the target portion is measured by the set of overlay marks of each exposure field to obtain first overlay data for the respective exposure field by a measuring system. The first overlay data is fed to form a second layer lithography pattern.
    Type: Application
    Filed: May 3, 2016
    Publication date: November 9, 2017
    Inventor: En-Chiuan Liou
  • Patent number: 9806031
    Abstract: A monitor method for process control in a semiconductor fabrication process is disclosed. A first alignment mark is formed in a layer on a substrate, and its position is measured and stored in a first measurement data. A fabrication process is then performed. Afterwards, another measurement is performed to measure the position of the first alignment mark and to generate a second measurement data. Finally, an offset value between the position of the first alignment mark in the first measurement data and those in the second measurement data is calculated.
    Type: Grant
    Filed: April 22, 2015
    Date of Patent: October 31, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: En-Chiuan Liou
  • Publication number: 20170309520
    Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a first metal gate and a second metal gate are formed on the substrate, in which the first metal gate includes a first work function metal layer, the second metal gate includes a second work function metal layer, the first metal gate and the second metal gate include different size, and the first work function metal layer and the second work function metal layer include different thickness.
    Type: Application
    Filed: May 19, 2016
    Publication date: October 26, 2017
    Inventors: En-Chiuan Liou, Chih-Wei Yang, Kuan-Ying Lai
  • Publication number: 20170294539
    Abstract: The present invention provides a semiconductor device, including a substrate, two gate structures disposed on a channel region of the substrate, an epitaxial layer disposed in the substrate between two gate structures, a first dislocation disposed in the epitaxial layer, wherein the profile of the first dislocation has at least two non-parallel slanting lines, and a second dislocation disposed adjacent to a top surface of the epitaxial layer, and the profile of the second dislocation has at least two non-parallel slanting lines.
    Type: Application
    Filed: June 21, 2017
    Publication date: October 12, 2017
    Inventors: En-Chiuan Liou, Yu-Cheng Tung
  • Patent number: 9772557
    Abstract: An illumination system includes a light source used to generate a light and an opaque plate. The opaque plate is disposed between the light source and a photomask and includes an annular aperture and an aperture dipole. The annular aperture has an inner side and an outer side. The aperture dipole includes at least one first aperture and at least one second aperture. The first aperture and the second aperture connected to the annular aperture respectively and protruding out from the outer side of the annular aperture are disposed symmetrically with respect to a center of the annular aperture.
    Type: Grant
    Filed: May 18, 2015
    Date of Patent: September 26, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Yu-Cheng Tung
  • Publication number: 20170263504
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a plurality of fin shaped structures and an insulating layer. The substrate has a fin field-effect transistor (finFET) region, a first region, a second region and a third region. The first region, the second region and the third region have a first surface, a second surface, and a third surface, respectively, where the first surface is relatively higher than the second surface and the second surface is relatively higher than the third surface. The fin shaped structures are disposed on a surface of the fin field-effect transistor region. The insulating layer covers the first surface, the second surface and the third surface.
    Type: Application
    Filed: May 25, 2017
    Publication date: September 14, 2017
    Inventors: En-Chiuan Liou, Yu-Cheng Tung
  • Patent number: 9761460
    Abstract: A method of fabricating a semiconductor structure is provided and includes the following steps. A semiconductor substrate including fin structures is provided. Each fin structure is partly located in a first region and partly located in a second region adjoining the first region. A fin remove process is performed for removing the fin structures in the second region. A fin cut process with a fin cut mask is performed for cutting a part of the fin structures in the first region. The fin cut mask includes cut patterns and a compensation pattern. The cut patterns are located corresponding to a part of the fin structures in the first region. The compensation pattern is located corresponding to the second region of the semiconductor substrate. A fin bump is formed in the second region and corresponding to the compensation pattern after the fin cut process and the fin remove process.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: September 12, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tang-Chun Weng, Chia-Ching Lin, Yen-Pu Chen, En-Chiuan Liou
  • Patent number: 9753373
    Abstract: A semiconductor processing method is provided and includes the following steps. A first semiconductor process is performed for a wafer to obtain plural overlay datum (x, y), wherein x and y are respectively shift values in X-direction and Y-direction. Next, A re-correct process is performed by a computer, wherein the re-correct process comprises: (a) providing an overlay tolerance value (A, B) and an original out of specification value (OOS %), wherein A and B are respectively predetermined tolerance values in X-direction and Y-direction; (b) providing at least a k value (kx, ky); (c) modifying the overlay datum (x, y) according to the k value (kx, ky) to obtain at least a revised overlay datum (x?, y?); and (d) calculating a process parameter from the revised overlay datum (x?, y?). Lastly, a second semiconductor process is performed according to the process parameter . . . . The present invention further provides a lithography system.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: September 5, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Chia-Hung Wang
  • Patent number: 9754841
    Abstract: The present invention provides a method of forming an integrated circuit including a substrate, a first transistor, a second transistor and a third transistor. The first transistor has a first metal gate including a first bottom barrier layer, a first work function metal layer and a first metal layer. The second transistor has a second metal gate including a second bottom barrier layer, a second work function metal layer and a second metal layer. The third transistor has a third metal gate including a third bottom barrier layer, a third work function metal layer and a third metal layer. The first transistor, the second transistor and the third transistor has the same conductive type. A nitrogen concentration of the first bottom barrier layer>a nitrogen concentration of the second bottom barrier layer>a nitrogen concentration of the third bottom barrier layer.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: September 5, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Wei Yang, Yu-Feng Liu, Jian-Cun Ke, Chia-Fu Hsu, Yu-Ru Yang, En-Chiuan Liou
  • Patent number: 9746786
    Abstract: An overlay mask includes a plurality of first patterns, a plurality of second patterns and a plurality of third patterns. The first patterns are arranged within a first pitch. The second patterns are arranged within a second pitch. A first portion of the third patterns are arranged alternately with the first patterns, within the first pitch, and a second portion of the third patterns are arranged alternately with the second patterns, within the second pitch, and the first pitch is not equal to the second pitch.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: August 29, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Che-Yi Lin, En-Chiuan Liou, Yi-Jing Wang, Chia-Hsun Tseng