Abstract: Disclosed is a passive display apparatus. The passive display apparatus includes multiple light-emitting elements, a scanning circuit, multiple scanning switches, and a current control circuit. The light emitting elements are arranged in an array. The scanning circuit is coupled to the light-emitting elements and has multiple scan shift registers to generate multiple scan signals enabled sequentially. The scanning switches receive the scan signals and a first operating voltage to provide the first operating voltage to the light-emitting elements row by row. The current control circuit is coupled to the light-emitting elements, and receives multiple pixel voltages to provide multiple light-emitting currents to the light-emitting elements. The light-emitting elements emit light based on the received light-emitting currents.

Abstract: A semiconductor device includes a first fin-shaped structure and a second fin-shaped structure on a substrate, a bump between the first fin-shaped structure and the second fin-shaped structure, a first recess between the first fin-shaped structure and the bump, and a second recess between the second fin-shaped structure and the bump. Preferably, a top surface of the bump includes a curve concave upward, a width of the bump is greater than twice the width of the first fin-shaped structure, and a height of the bump is less than one fourth of the height of the first fin-shaped structure.

Abstract: A method for filling a gap includes: filling a dielectric layer in the gap so that a seam is formed in the dielectric layer, the dielectric layer including two surface portions at two opposite sides of the seam, respectively; introducing a surface modification agent into the seam such that each of the two surface portions has first functional groups and second functional groups; forming a stress layer on the dielectric layer to cover the seam, the stress layer including a material different from that of the dielectric layer; and applying an energy field to permit the two surface portions to bond with each other through reaction between the first functional groups and the second functional groups.

Abstract: A semiconductor memory device includes pairs of metal lines and memory arrays. Each of the memory arrays includes first and second sets of thin film transistors (TFTs), a first switch transistor, and a second switch transistor. The TFTs in the first and second sets are electrically connected to each other in parallel. The first switch transistor is electrically connected in series to one of the TFTs in the first set and one of the metal lines in a corresponding one of the pairs of the metal lines. The second switch transistor is electrically connected in series to one of the TFTs in the second set and the other one of the metal lines in the corresponding one of the pairs of the metal lines.

Abstract: A memory device is disclosed. The memory device includes a plurality of memory cells, each of the memory cells including an access transistor and a resistor coupled to each other in series. The resistors of the memory cells are each formed as one of a plurality of interconnect structures disposed over a substrate. The access transistors of the memory cells are disposed opposite a first metallization layer containing the plurality of interconnect structures from the substrate.

Abstract: A display panel includes a driving backplane, a light emitting component, a reflective structure and a bridging component. The driving backplane has a first pad and a second pad separated from each other. The light emitting component has a first electrode and a second electrode. The first electrode is electrically connected to the first pad of the driving backplane, and the first electrode is located between the second electrode and the first pad of the driving backplane. The reflective structure is disposed on the driving backplane and located at a periphery of the light emitting component. The bridging component is disposed on the light emitting component. One end of the bridging component is electrically connected to the second electrode. The bridging component passes across at least one portion of the reflective structure. The other end of the bridging component is electrically connected to the second pad of the driving backplane.

Abstract: A memory device includes a first layer, wherein the first layer includes a first memory array, a first row decoder circuit, and a first column sensing circuit. The memory device includes a second layer disposed with respect to the first layer in a vertical direction. The second layer includes a first peripheral circuit operatively coupled to the first memory array, the first row decoder circuit, and the first column sensing circuit. The memory device includes a plurality of interconnect structures extending along the vertical direction. At least a first one of the plurality of interconnect structures operatively couples the second layer to the first layer.

Abstract: A semiconductor device includes a substrate, a gate stack, and epitaxy structures. The substrate has a P-type region. The gate stack is over the P-type region of the substrate and includes a gate dielectric layer, a bottom work function (WF) metal layer, a top WF metal layer, and a filling metal. The bottom WF metal layer is over the gate dielectric layer. The top WF metal layer is over and in contact with the bottom WF metal layer. Dipoles are formed between the top WF metal layer and the bottom WF metal layer, and the dipoles direct from the bottom WF metal layer to the top WF metal layer. The filling metal is over the top WF metal layer. The epitaxy structures are over the P-type region of the substrate and on opposite sides of the gate stack.

Abstract: A digital compute-in-memory (DCIM) macro includes a memory cell array and an arithmetic logic unit (ALU). The memory cell array stores weight data of a neural network. The ALU receives parallel bits of a same input channel in an activation input, and generates a convolution computation output of the parallel bits and target weight data in the memory cell array.

Abstract: A digital compute-in-memory (DCIM) system includes a first DCIM macro. The first DCIM macro includes a first memory cell array and a first arithmetic logic unit (ALU). The first memory cell array has N rows that are configured to store weight data of a neural network in a single weight data download session, wherein N is a positive integer not smaller than two. The first ALU is configured to receive a first activation input, and perform convolution operations upon the first activation input and a single row of weight data selected from the N rows of the first memory cell array to generate first convolution outputs.

Abstract: An integrated circuit includes a sense amplifier connected to a bit line and a bit line bar, a first memory cell configured to store a data signal and selectively output the data signal on at least one of the bit line and the bit line bar in response to a word line signal, a first circuit connected between a first voltage terminal configured to receive a first external voltage and the bit line and having a first enable terminal configured to receive a first enable signal, wherein the first external voltage is different than the data signal, and a second circuit connected between a second voltage terminal configured to receive a second external voltage and the bit line bar and having a second enable terminal configured to receive a second enable signal, wherein the second external voltage is different than the data signal and the first external voltage.

Abstract: An image processing method for a video processor, for generating an extrapolated frame according to a previous frame and a current frame, includes steps of: projecting a plurality of motion vectors (MVs) to the extrapolated frame subsequent to the current frame; determining whether a block of the extrapolated frame is projected by at least two of the MVs; selecting at least two candidate MVs from the MVs projected to the block when the block is projected by at least two of the MVs; calculating a blended MV which is a mixture of the at least two candidate MVs, and projecting the blended MV to the previous frame; obtaining a reference MV corresponding to position of the previous frame projected by the blended MV; and comparing the reference MV with the at least two candidate MVs, to select a final MV for the block from the at least two candidate MVs.

Abstract: A door locking mechanism and semiconductor container using the same include door panel, cover, and locking module. The door panel has a first stop structure. The cover and the door panel define an accommodating space for receiving the locking module. The locking module includes rotating member, holding member, and elastic member. The elastic member is disposed on the holding member and has a second stop structure near the first stop structure. The elastic member is disposed between the holding and the rotating member. The elastic member is compressed when a force is applied to the holding member, and the second stop structure detaches from a limitation state with the first stop structure for allowing a rotating operation of the rotating member. The elastic member elastically restores when the force is removed, and the second stop structure returns to the limitation state for limiting the rotating operation.

Abstract: A button mechanism is provided, including a frame, a motor disposed on the frame, a rotary member connected to the motor, a protrusion disposed on the rotary member, and a movable member hinged to the frame. When the movable member moves relative to the frame in the first direction, the protrusion contacts the movable member, and the rotary member is driven by the motor to rotate, whereby the movable member is pushed back by the protrusion so that it moves in the second direction, which is the opposite of the first direction.

Abstract: A semiconductor device includes a first memory cell that includes: a first conductor structure extending along a first lateral direction; a first portion of a first memory film wrapping around a first portion of the first conductor structure; a first semiconductor film wrapping around the first portion of the first memory film; a second conductor structure extending along a vertical direction and coupled to a first sidewall of the first semiconductor film, wherein the first sidewall faces toward or away from a second lateral direction perpendicular to the first lateral direction; and a third conductor structure extending along the vertical direction and coupled to a second sidewall of the first semiconductor film, wherein the second sidewall faces toward or away from the second lateral direction.

Abstract: A memory circuit includes a plurality of bitcells coupled to a plurality of bitlines, a plurality of wordlines, a plurality of source lines, and a control line. A first of the bitcells and a second of the bitcells are coupled to a first of the bitlines. The first bitcell is coupled to a first of the source lines. The second bitcell is coupled to a second of the source lines. The first source line is different from the second source line.

Abstract: An integrated circuit includes a memory cell array, a row decoder configured to generate a first decoder signal, a column decoder configured to generate a second decoder signal, and an array of write assist circuits coupled to the row and column decoder and the memory cell array. Each write assist circuit is configured to set an operating voltage of a corresponding memory cell, and generate the output signal in response to a first control signal. The operating voltage corresponds to an output signal. Each write assist circuit includes an AND gate coupled to a programmable voltage tuner. The programmable voltage tuner includes a set of P-type transistors coupled to a first P-type transistor. The set of P-type transistors is coupled together in parallel, and receives a set of select control signals. A first terminal of the first P-type transistor is configured to receive an AND signal from the AND gate.

Abstract: A temperature-sensitive cell culture composition is provided. The temperature-sensitive cell culture composition includes a hydrogel, a cellulose, a gelatin and a collagen. Based on 1 part by weight of the collagen, a content of the hydrogel is between 0.03 parts by weight and 60 parts by weight, a content of the cellulose is between 150 parts by weight and 360 parts by weight, and a content of the gelatin is between 21 parts by weight and 12 parts by weight. In addition, a method for using the temperature-sensitive cell culture composition, a method for forming the temperature-sensitive cell culture composition, and a use of the temperature-sensitive cell culture composition are also provided.

Abstract: A semiconductor device includes a first transistor, a second transistor, and a memory component. The first transistor includes a first silicon layer, a high-k gate dielectric layer above the first silicon layer, a first metal gate above the high-k gate dielectric layer, and first source/drain regions within the first silicon layer. The second transistor includes a second silicon layer, a first silicon oxide layer above the second silicon layer, a plurality of first doped silicon gates above the first silicon oxide layer, a plurality of second doped silicon gates above the first silicon oxide layer and alternately arranged with the plurality of first doped silicon gates, and second source/drain regions within the second silicon layer. The memory component is above the first and second transistors, and electrically coupled to the second source or drain region.

Abstract: A semiconductor device includes first nanostructures vertically separated from one another, a first gate structure wrapping around each of the first nanostructures, and second nanostructures vertically separated from one another. The semiconductor device also includes a second gate structure wrapping around the second nanostructures, a first drain/source structure coupled to a first end of the first nanostructures, a second drain/source structure coupled to both of a second end of the first nanostructures and a first end of the second nanostructures, and a third drain/source structure coupled to a second end of the second nanostructures. The first drain/source structure has a first doping type, the second and third drain/source structures have a second doping type, and the first doping type is opposite to the second doping type.