Abstract: Different embodiments of local redundancy decoder circuits that can be used in a memory device are disclosed. The different types of local redundancy decoder circuits are operably connected to the columns of memory cells in a memory array.

Abstract: A device includes a substrate, a first sense amplifier disposed on the substrate, a first word line driver disposed on the substrate and situated adjacent the first sense amplifier in the x-direction, and a first memory array disposed above the first sense amplifier and above the first word line driver in the z-direction. A plurality of first conductive segments extend alternately in the x-direction and the y-direction, and are disposed between the first memory array and the first sense amplifier and configured to electrically connect the first sense amplifier to a first bit line of the first memory array. A plurality of second conductive segments extend alternately in the x-direction and the y-direction, and are disposed between the first memory array and the first word line driver and configured to electrically connect the first word line driver to a first word line of the first memory array.

Abstract: The present teachings relate to a method for improving a production process for manufacturing a chemical product at an industrial plant comprising at least one equipment and one or more computing units, and the product being manufactured by processing at least one input material, which method comprises: receiving real-time process data from the equipment; determining a subset of the real-time process data; computing at least one state related to the input material and/or the equipment. The present teachings also relate to a system for improving the production process, a use, and a software program.

Abstract: Header circuitry for a memory device includes multiple backside power rails that form distinct voltage sources for a plurality of switching devices in the header circuitry. The header circuitry includes at least one region of a first conductivity type. A first section in the first region includes one backside power rail (BPR) that forms a first voltage source that provides a first voltage. A second section in the same first region includes another BPR that forms a second voltage source that provides a second voltage that is different from the first voltage.

Abstract: A method (of reading a ferroelectric field-effect transistor (FeFET) configured as a 2-bit storage device that stores two bits, wherein the FeFET includes a first source/drain (S/D) terminal, a second S/D terminal, a gate terminal and a ferroelectric layer, a second bit being at a first end of the ferroelectric layer, the first end being proximal to the first S/D terminal) includes reading the second bit including: applying a gate sub-threshold voltage to the gate terminal; applying a read voltage to the second S/D terminal; applying a do-not-disturb voltage to the first S/D terminal; and sensing a first current at the second S/D terminal; and wherein the read voltage is lower than the do-not-disturb voltage.

Abstract: A method of forming a storage cell includes: forming a transistor on a semiconductor substrate; forming a plurality of fuses in at least one conductive layer on the semiconductor substrate to couple a connecting terminal of the transistor; forming a bit line to couple the plurality of fuses; and forming a word line to couple a control terminal of the transistor.

Abstract: A semiconductor device comprises a first conductive structure extending along a vertical direction and a second conductive structure extending along the vertical direction. The second conductive structure is spaced apart from the first conductive structure along a lateral direction. The semiconductor device further comprises a plurality of third conductive structures each extending along the lateral direction. The plurality of third conductive structures are disposed across the first and second conductive structures. The first and second conductive structures each have a varying width along the lateral direction. The plurality of third conductive structures have respective different thicknesses in accordance with the varying width of the first and second conductive structures.

Abstract: A method of operating a memory circuit includes turning on a first programming device and turning on a first selection device thereby causing a first current to flow through a first fuse element. The first fuse element is coupled between the first selection device and the first programming device. The method further includes turning off a second programming device and turning off a second selection device, and blocking the first current from flowing through a second fuse element that is coupled between the second selection device and the first programming device.

Abstract: A semiconductor device includes a memory structure comprising a plurality of first memory cells. The semiconductor device includes a test structure disposed next to the memory structure and comprising a first monitor pattern. The plurality of first memory cells, arranged along a first lateral direction, that have a plurality of first channel films extending along a vertical direction, respectively, and share a first ferroelectric film extending along the vertical direction and the first lateral direction. The first monitor pattern includes: (a) a second channel film extending along the vertical direction and the first lateral direction; and (b) a second ferroelectric film extending along the vertical direction and the first lateral direction.

Abstract: A memory cell includes: a first transistor, having a first diffusion region coupled to a bit line and a first gate electrode coupled to a first word line; a second transistor, having a second diffusion region coupled to the bit line and a second gate electrode coupled to a second word line; and a third transistor, having a third diffusion region coupled to a fourth diffusion region of the first transistor, a fifth diffusion region coupled to a sixth diffusion region of the second transistor, and a third gate electrode coupled to a third word line; wherein the first transistor is arranged to have a first threshold voltage, the second transistor is arranged to have a second threshold voltage, and the second threshold voltage is different from the first threshold voltage.

Abstract: The present teachings relate to a method for monitoring and/or controlling a production process for manufacturing at least one industrial product at an industrial plant comprising at least one equipment by processing at least one input, the method comprising: receiving, via an input inter-face, real-time process data from the equipment; determining, via the computing unit, a subset of the real-time process data; providing as output data the subset of the real-time process data. The present teachings also relate to a system, a use, and a software product.

Abstract: A multi-fuse memory cell is disclosed. The circuit includes: a first fuse element electrically coupled to a first transistor, a gate of the first transistor is electrically coupled to a first selection signal; a second fuse element electrically coupled to a second transistor, a gate of the second transistor is electrically coupled to a second selection signal, both the first transistor and the second transistor are grounded; and a programming transistor electrically coupled to the first fuse element and the second fuse element, wherein a gate of the programming transistor is electrically coupled to a programming signal.

Abstract: An integrated circuit includes a front-side horizontal conducting line in a first metal layer, a front-side vertical conducting line in a second metal layer, a front-side fuse element, and a backside conducting line. The front-side horizontal conducting line is directly connected to the drain terminal-conductor of a transistor through a front-side terminal via-connector. The front-side vertical conducting line is directly connected to the front-side horizontal conducting line through a front-side metal-to-metal via-connector. The front-side fuse element having a first fuse terminal conductively connected to the front-side vertical conducting line. The backside conducting line is directly connected to the source terminal-conductor of the transistor through a backside terminal via-connector.

Abstract: A semiconductor die comprises: a first semiconductor device and a second semiconductor device. The first semiconductor device comprises a first device portion comprising a first sub-array of memory devices, and a first interface portion located adjacent to the first device portion in a first direction. The first interface portion has a staircase profile in a vertical direction. The second semiconductor device comprises a second device portion adjacent to the first device portion in the first direction opposite the first interface portion. The second device portion comprises a second sub-array of memory devices, and a second interface portion located adjacent to the first device portion in the first direction opposite the first interface portion. The second interface portion also has a staircase profile in the vertical direction. The first semiconductor device is electrically isolated from the second semiconductor device.

Abstract: A semiconductor device includes a first conductor structure extending along a lateral direction. The semiconductor device includes a first memory film that extends along a vertical direction and is in contact with the first conductor structure. The semiconductor device includes a first semiconductor film that extends along the vertical direction and is in contact with the first memory film. Ends of the first semiconductor film align with ends of the first memory film, respectively. The semiconductor device includes a second conductor structure extending along the vertical direction. The semiconductor device includes a third conductor structure extending along the vertical direction. The semiconductor device includes a fourth conductor structure extending along the vertical direction. The second and fourth conductor structures are coupled to the ends of the first semiconductor film, and the third conductor structure is coupled to a portion of the first semiconductor film between its ends.

Abstract: A memory device includes a plurality of word lines (WLs). The memory device includes a plurality of drivers that are each configured to control a corresponding one of the plurality of WLs and each comprise a first transistor having a first conductive type and a second transistor having a second conductive type. The first transistor of a first one of the drivers is formed in a first well of a substrate, and the second transistor of the first driver is formed in a second well of the substrate. The first well is spaced apart from the second well.

Abstract: A memory device includes a plurality of first memory cells disposed along a vertical direction. Each of the plurality of first memory cells includes a portion of a first channel segment that extends along the vertical direction and has a first sidewall and a second sidewall. The first and second sidewalls of the first channel segment facing toward and away from a first lateral direction, respectively. Each of the plurality of first memory cells includes a portion of a first ferroelectric segment that also extends along the vertical direction and is in contact with the first sidewall of the first channel segment. A width of the first ferroelectric segment along a second lateral direction is different from a width of the first channel segment along the second lateral direction. The second lateral direction is perpendicular to the first lateral direction.

Abstract: Disclosed herein are related to a device for performing neuromorphic computing. In one aspect, a device includes a back end of line layer including a three-dimensional memory array. The three-dimensional memory array may include a plurality of memory cells to store a plurality sets of weight values of a neural network model. In one aspect, the device includes a front end of line layer including a controller. The controller may apply one or more input voltages corresponding to an input to the neural network model to the three-dimensional memory array, and receive one or more output voltages from the three-dimensional memory array to perform computations of the neural network model.

Abstract: Disclosed herein are related to a memory array. In one aspect, the memory array includes a first set of memory cells including a first subset of memory cells and a second subset of memory cells. In one aspect, the memory array includes a first switch including a first electrode connected to first electrodes of the first subset of memory cells, and a second electrode connected to a first global line. In one aspect, the memory array includes a second switch including a first electrode connected to first electrodes of the second subset of memory cells, and a second electrode connected to the first global line.

Abstract: A method includes: forming an interconnect structure over a substrate, the forming of the interconnect structure includes forming a memory device including a transistor. The forming of the interconnect structure includes: forming a first metallization layer and a second metallization layer over the first metallization layer; forming a gate region of the transistor in at least one of the first and second metallization layers; etching a trench disposed in the second metallization layer and exposing the gate region; depositing a gate dielectric layer in the trench over the gate region; depositing a channel layer in the trench over the gate dielectric layer; and forming two source/drain regions of the transistor over the channel layer on opposite sides of the trench. At least one of the gate region and the channel layer includes two first segments extending in the trench, wherein the first segments are parallel with each other.