Patents by Inventor En Huang
En Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11889835Abstract: The present invention relates to a plant growth regulator of elevating anti-stress ability and use thereof. The plant growth regulator, which is consisted of Lactobacillus fermenting culture solution, has excellent thermostability and safety without any side effect, significantly elevating ability against biotic and abiotic stresses. Therefore, the Lactobacillus fermenting culture solution can be applied as the plant growth regulator or a use in preparation of a composition for elevating anti-stress ability of a plant.Type: GrantFiled: March 25, 2019Date of Patent: February 6, 2024Assignee: GENMONT BIOTECH INCORPORATIONInventors: Yi-Hsing Chen, Wan-Hua Tsai, Tsuei-Yin Huang, Hsiang-En Huang, Yu-Jen Hsu
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Publication number: 20240024839Abstract: The present teachings relate to a method for monitoring a production process for manufacturing a chemical product at an industrial plant, the method comprising: providing an up-stream object identifier comprising input material data, receiving real-time process data from one or more of the equipment zones; determining a subset of the real-time process data based on the upstream object identifier and a zone presence signal; computing at least one zone-specific performance parameter of the chemical product related to the up-stream object identifier based on the subset of the real-time process data and historical data; appending, to the upstream object identifier, the at least one zone-specific performance parameter. The present teachings also relate to a system for monitoring a production process, a dataset, use, a method for generating the dataset and a software program for the same.Type: ApplicationFiled: September 16, 2021Publication date: January 25, 2024Inventors: Christian-Andreas Winkler, Hans Rudolph, Michael Hartmann, Markus Rautenstrauch, Yuan En Huang, Sebastian Wandernoth, Nataliya Yakut
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Publication number: 20240032274Abstract: A memory device includes a semiconductor substrate. The memory device includes a stack of channel layers over the semiconductor substrate, each channel layer including an oxide material. The memory device includes a word line structure interleaved with the stack of channel layers. The memory device includes a source feature and a drain feature on both sides of the stack of channel layers.Type: ApplicationFiled: January 30, 2023Publication date: January 25, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Peng-Chun Liou, Chia-En Huang, Ya-Yun Cheng, Chung-Wei Wu
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Publication number: 20240021220Abstract: Disclosed herein are related to a memory array including a set of memory cells and a set of switches to configure the set of memory cells. In one aspect, each switch is connected between a corresponding local line and a corresponding subset of memory cells. The local clines may be connected to a global line. Local lines may be metal rails, for example, local bit lines or local select lines. A global line may be a metal rail, for example, a global bit line or a global select line. A switch may be enabled or disabled to electrically couple a controller to a selected subset of memory cells through the global line. Accordingly, the set of memory cells can be configured through the global line rather than a number of metal rails to achieve area efficiency.Type: ApplicationFiled: July 28, 2023Publication date: January 18, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Meng-Sheng Chang, Chia-En Huang, Yi-Ching Liu, Yih Wang
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Publication number: 20240021772Abstract: An optoelectronic semiconductor device is provided. The optoelectronic semiconductor device includes an epitaxial stack, a trench, a concave portion, a first contact structure, and a first electrode. The epitaxial stack includes a first semiconductor structure, an active structure on the first semiconductor structure, and a second semiconductor structure on the active structure, wherein the epitaxial stack has a first portion and a second portion, and the second semiconductor structure of the first portion is separated from the second semiconductor structure of the second portion. The trench is located between the first portion and the second portion. The concave portion is located in the first portion. The first contact structure is located in the concave portion. The first electrode covers the first contact structure. When the optoelectronic semiconductor device is operating, the first portion does not emit light.Type: ApplicationFiled: July 14, 2023Publication date: January 18, 2024Inventors: Ching-En Huang, Hao-Ming Ku, Shih-I Chen, Tzu-Ling Yang, Ya-Wen Lin, Chuang-Sheng Lin, Yi-Chia Ho
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Publication number: 20240012395Abstract: A method can be used for controlling a downstream production process for manufacturing an article at a downstream industrial plant, by processing at least one thermoplastic polyurethane (“TPU”) and/or expanded thermoplastic polyurethane (“ETPU”) material using the downstream production process. The method involves providing, at a downstream computing unit, a set of downstream control settings for controlling the production of the article. The downstream control settings are determined based on a downstream object identifier; at least one desired downstream performance parameter related to the article; and downstream historical data. The set of downstream control settings is usable for manufacturing the article at the downstream industrial plant. A corresponding system for downstream production, use, and software product are provided.Type: ApplicationFiled: September 16, 2021Publication date: January 11, 2024Applicant: BASE SEInventors: Christian-Andreas WINKLER, Hans Rudolph, Michael Hartmann, Markus Rautenstrauch, Yuan En Huang, Nataliya Yakut, Sebastian Wandermoth
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Publication number: 20240015976Abstract: In an embodiment, a device includes a first gate structure over a substrate, the first gate structure including a first gate electrode over a first side of a first gate dielectric; a first electrode and a second electrode disposed over a second side of the first gate dielectric opposite the first side; a second gate structure disposed between the first electrode and the second electrode, the second gate structure including a second gate electrode and a second gate dielectric, the second gate dielectric at least laterally surrounding the second gate electrode; and a semiconductor film disposed between the first electrode and the second electrode and at least laterally surrounding the second gate structure, wherein at least one of the first gate dielectric or the second gate dielectric is a memory film.Type: ApplicationFiled: January 10, 2023Publication date: January 11, 2024Inventors: Meng-Han Lin, Sai-Hooi Yeong, Chia-En Huang, Chi On Chui
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Patent number: 11869971Abstract: A FeFET configured as a 2-bit storage device that includes a gate stack including a ferroelectric layer over a semiconductor substrate; and the ferroelectric layer includes dipoles; and a first set of dipoles at the first end of the ferroelectric layer has a first polarization; and a second set of dipoles at the second end of the ferroelectric layer has a second polarization, the first and second polarizations of the corresponding first and second sets of dipoles representing storage of 2 bits, wherein a first bit of the 2-bit storage device being configured to be read by application of a read voltage to the source region and a do-not-disturb voltage to the drain region; and a second bit of the 2-bit storage device being configured to be read by application of the do-not-disturb voltage to the source region and the read voltage to the drain region.Type: GrantFiled: December 15, 2022Date of Patent: January 9, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Meng-Han Lin, Chia-En Huang, Han-Jong Chia, Martin Liu, Sai-Hooi Yeong, Yih Wang
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Publication number: 20240006348Abstract: A method for fabricating memory devices includes forming a first portion of a memory device that includes a first device portion and one or more first interface portions. The first device portion includes a plurality of first memory strings, each of which includes a plurality of first memory cells vertically separated from one another. Each of the one or more first interface portions, laterally abutted to one side of the first device portion, includes a plurality of first word lines (WLs). The method further includes forming a plurality of first source lines (SLs) and a plurality of first bit lines (BLs) in the first device portion. The method further includes forming a first seal ring structure that laterally encloses both the first device portion and the first interface portion concurrently with forming the pluralities of SLs and BLs.Type: ApplicationFiled: July 28, 2023Publication date: January 4, 2024Applicant: Taiwan Semiconductor Manfuacturing Company, Ltd.Inventors: Meng-Han Lin, Chia-En Huang
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Publication number: 20230422510Abstract: A semiconductor device includes a word line (WL) structure. The semiconductor device includes a ferroelectric layer over the WL structure. The semiconductor device includes a channel layer over the ferroelectric layer. The semiconductor device includes a source line (SL) structure over the channel layer. The semiconductor device includes a bit line (BL) structure over the channel layer. The BL structure includes a portion that laterally extends toward the SL structure. The semiconductor device further includes a dielectric layer laterally interposed between the SL structure and the BL structure.Type: ApplicationFiled: February 15, 2023Publication date: December 28, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Meng-Han Lin, Chia-En Huang, Sai-Hooi Yeong
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Publication number: 20230422512Abstract: A memory device includes a first memory array including: a plurality of memory strings spaced from each other along a first lateral direction and a second lateral direction, each of the plurality of memory strings including a plurality of memory cells arranged along a vertical direction; and a plurality of first conductive structures extending along the vertical direction; wherein each of the plurality of first conductive structures includes a first portion and a second portion; wherein the first portion extends across the plurality of memory cells of a corresponding pair of the plurality of memory strings along the vertical direction, and the second portion is disposed over the first portion along the vertical direction; and wherein the second portion extends farther than the first portion along at least one of the first or second lateral direction.Type: ApplicationFiled: July 31, 2023Publication date: December 28, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-En Huang, Meng-Han Lin, Ya-Hui Wu
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Patent number: 11856762Abstract: A memory device includes a first transistor. The first transistor includes one or more first semiconductor nanostructures spaced apart from one another along a first direction. Each of the one or more first semiconductor nanostructures has a first width along a second direction perpendicular to the first direction. The memory device also includes a second transistor coupled to the first transistor in series. The second transistor includes one or more second semiconductor nanostructures spaced apart from one another along the first direction. Each of the one or more second semiconductor nanostructures has a second, different width along the second direction.Type: GrantFiled: January 20, 2023Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Meng-Sheng Chang, Chia-En Huang, Yi-Hsun Chiu, Yih Wang
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Patent number: 11854663Abstract: A method of operating a memory circuit includes enabling a first row of select transistors, disabling a second row of select transistors, enabling a first row of memory cells in response to a first word line signal, and disabling a second row of memory cells in response to a second word line signal. Enabling the first row of select transistors includes turning on a first select transistor in the first row of select transistors in response to a first select line signal thereby electrically coupling a first local bit line and a global bit line to each other. Disabling the second row of select transistors includes turning off a second select transistor in the second row of select transistors in response to a second select line signal thereby electrically decoupling a second local bit line and the global bit line from each other.Type: GrantFiled: July 26, 2022Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yi-Ching Liu, Chia-En Huang, Yih Wang
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Patent number: 11854616Abstract: Disclosed herein are related to a memory array. In one aspect, the memory array includes a set of resistive storage circuits including a first subset of resistive storage circuits connected between a first local line and a second local line in parallel. The first local line and the second local line may extend along a first direction. In one aspect, for each resistive storage circuit of the first subset of resistive storage circuits, current injected at a first common entry point of the first local line exits through a first common exit point of the second local line, such that each resistive storage circuit of the first subset of resistive storage circuits may have same or substantial equal resistive loading.Type: GrantFiled: August 28, 2021Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Meng-Sheng Chang, Chia-En Huang, Yi-Ching Liu, Yih Wang
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Patent number: 11856768Abstract: A memory device includes a substrate, a first transistor and a second transistor, a Schottky diode, a first word line, a second word line, and a bit line. The first transistor and the second transistor are over the substrate, wherein a first source/drain structure of the first transistor is electrically connected to a first source/drain structure of the second transistor. The Schottky diode is electrically connected to a gate structure of the first transistor. The first word line is electrically connected to the gate structure of the first transistor through the Schottky diode. The second word line is electrically connected to a gate structure of the second transistor. The bit line is electrically connected to a second source/drain structure of the second transistor.Type: GrantFiled: May 23, 2022Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsin-Wen Su, Chia-En Huang, Shih-Hao Lin, Lien-Jung Hung, Ping-Wei Wang
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Patent number: 11854914Abstract: A memory device includes a first memory block. The first memory block includes a first memory sub-array and a first interface portion disposed next to the first memory sub-array. The first memory block further includes a plurality of first interconnect structures electrically coupled to the first memory sub-array through the first interface portion, and a second plurality of interconnect structures configured to electrically couple a corresponding one of the plurality of first interconnect structures to a transistor. The memory device further includes a first test structure and a second test structure disposed next to the first memory block, each configured to simulate electrical connections of the plurality of second interconnect structures. The first and second test structures are electrically coupled to each other and are each electrically isolated form the first memory block.Type: GrantFiled: November 15, 2021Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Meng-Han Lin, Chia-En Huang
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Patent number: 11856783Abstract: A semiconductor device comprises a first conductive structure extending along a vertical direction and a second conductive structure extending along the vertical direction. The second conductive structure is spaced apart from the first conductive structure along a lateral direction. The semiconductor device further comprises a plurality of third conductive structures each extending along the lateral direction. The plurality of third conductive structures are disposed across the first and second conductive structures. The first and second conductive structures each have a varying width along the lateral direction. The plurality of third conductive structures have respective different thicknesses in accordance with the varying width of the first and second conductive structures.Type: GrantFiled: August 26, 2021Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Peng-Chun Liou, Ya-Yun Cheng, Yi-Ching Liu, Meng-Han Lin, Chia-En Huang
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Patent number: 11856761Abstract: A semiconductor device includes first nanostructures vertically separated from one another, a first gate structure wrapping around each of the first nanostructures, and second nanostructures vertically separated from one another. The semiconductor device also includes a second gate structure wrapping around the second nanostructures, a first drain/source structure coupled to a first end of the first nanostructures, a second drain/source structure coupled to both of a second end of the first nanostructures and a first end of the second nanostructures, and a third drain/source structure coupled to a second end of the second nanostructures. The first drain/source structure has a first doping type, the second and third drain/source structures have a second doping type, and the first doping type is opposite to the second doping type.Type: GrantFiled: September 16, 2021Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Meng-Sheng Chang, Chia-En Huang, Chun Chung Su, Wen-Hsing Hsieh
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Patent number: 11856796Abstract: A semiconductor device includes a lower silicon layer comprising a first area and a second area. The lower silicon layer in the first area includes a first silicon oxide layer, a first upper silicon layer disposed above the first silicon oxide layer, and a first metal gate disposed above the first upper silicon layer. The lower silicon layer in the second area includes a second silicon oxide layer, a plurality of first doped silicon gates disposed above the second silicon oxide layer, and a plurality of portions of a second doped silicon gate disposed above the second silicon oxide layer. The plurality of first doped silicon gates and the plurality of portions of the second doped silicon gate are alternatively arranged with each other. The lower silicon layer in the second area also includes a plurality of second metal gates disposed directly above the plurality of first doped silicon gates, respectively.Type: GrantFiled: January 27, 2022Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Meng-Han Lin, Chia-En Huang
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Publication number: 20230413572Abstract: A semiconductor structure includes an isolation layer; first and second source/drain (S/D) metal electrodes over the isolation layer; a metal gate disposed laterally between the first and the second S/D metal electrodes; a ferroelectric layer on a bottom surface and sidewall surfaces of the metal gate; and an oxide semiconductor layer. The oxide semiconductor layer includes a first portion under the first and the second S/D metal electrodes; a second portion under the ferroelectric layer and being thicker than the first portion; third portions above the first and the second S/D metal electrodes, respectively; and fourth portions on sidewalls of the first and the second S/D metal electrodes, respectively, and connecting the third portions to the second portion.Type: ApplicationFiled: August 24, 2022Publication date: December 21, 2023Inventors: Meng-Han Lin, Chia-En Huang