Abstract: A semiconductor device is disclosed. The semiconductor device includes a fin-based structure formed on a substrate. The semiconductor device includes a plurality of first nanosheets, vertically spaced apart from one another, that are formed on the substrate. The semiconductor device includes a first source/drain (S/D) region electrically coupled to a first end of the fin-based structure. The semiconductor device includes a second S/D region electrically coupled to both of a second end of the fin-based structure and a first end of the plurality of first nanosheets. The semiconductor device includes a third S/D region electrically coupled to a second end of the plurality of first nanosheets. The fin-based structure has a first crystal lattice direction and the plurality of first nanosheets have a second crystal lattice direction, which is different from the first crystal lattice direction.

Abstract: An integrated circuit read only memory (ROM) structure includes a first ROM transistor with a first gate electrode, a first source, and a first drain, and a second ROM transistor with a second gate electrode, a second source, and a second drain. A drain conductive line is over the first drain and the second drain, and is between the first drain and the second drain. The first drain, the drain conductive line and the second drain are between the first gate electrode and the second gate electrode, and a first trench isolation structure electrically isolates the first drain from the first source is below the first gate electrode.

Abstract: A semiconductor device comprises a source and a pair of drains disposed on either side of the source in a first direction and spaced apart therefrom. A channel layer extending in the first direction is disposed on at least one radially outer surface of the source and the pair of drains in a second direction perpendicular to the first direction. A memory layer extending in the first direction is disposed on a radially outer surface of the channel layer in the second direction. At least one gate layer that extends in the first direction, is disposed on a radially outer surface of the memory layer in the second direction. A gate extension structure extends from the each of the drains at least part way towards the source in the first direction, and is located proximate to, and in contact with each of the channel layer and the corresponding drain.

Abstract: Header circuitry for a memory device includes multiple backside power rails that form distinct voltage sources for a plurality of switching devices in the header circuitry. The header circuitry includes at least one region of a first conductivity type. A first section in the first region includes one backside power rail (BPR) that forms a first voltage source that provides a first voltage. A second section in the same first region includes another BPR that forms a second voltage source that provides a second voltage that is different from the first voltage.

Abstract: A memory cell includes a transistor and a capacitor. The transistor includes a gate electrode, a gate dielectric disposed over the gate electrode, a channel feature disposed over the gate dielectric and overlapping the gate electrode, a source electrode disposed over the channel feature and electrically connected to the capacitor, and two drain electrodes disposed over the channel feature. The drain electrodes are disposed at opposite sides of the source electrode. The channel feature has a first channel portion extending between and interconnecting one drain electrode and the source electrode, and a second channel portion extending between and interconnecting the other drain electrode and the source electrode. The gate electrode overlaps both of the first channel portion and the second channel portion of the channel feature.

Abstract: A semiconductor device includes a substrate, an active structure, a memory structure, and a first conductive line. The active structure is disposed on the substrate. The memory structure is disposed over the active structure, and has a lower surface and an upper surface opposite to each other. The memory structure includes a deep via disposed in the memory structure, and extends in an upward direction from the lower surface to terminate at the upper surface. The first conductive line is disposed above the upper surface of the memory structure, and extends in a first lengthwise direction transverse to the upward direction. The first conductive line is electrically connected to the active structure through the deep via. A method for manufacturing the semiconductor device is also disclosed.

Abstract: The method includes forming a multi-layered stack having insulating layers and spacer layers alternately stacked on top of each other in a vertical direction over a substrate in a chip area having a first memory region and a second memory region; forming a first mask layer covering the second memory region, while leaving the first memory region partially exposed; etching the multi-layered stack to form first trenches in the first memory region; forming first gate layers, a first memory layer, and a first channel layer; removing the first mask layer; forming a second mask layer covering the first memory region, while leaving the second memory region partially exposed; etching the multi-layered stack to form second trenches; forming second gate layers, a second memory layer, and a second channel layer in the second trenches.

Abstract: A fleet vehicle management system includes an edge device disposed in a vehicle and a cloud device. A processing module of the edge device acquires around-view image and determines at least one traffic indication accordingly. The nearing event warning module of the edge device sends out a nearing event alert to a driver via an output module. The after event detection module of the edge device acquires GPS informations in a first time interval and a second time interval respectively to determine whether the vehicle meets an after event criterion. A violation event is triggered if the after event criterion is met. A database of the cloud device stores the nearing event alert, a driving violation result and a driving record information. The driver behavior analysis module generates an information for evaluating a driving score based on the nearing event, the violation event and the driving record information.

Abstract: The present invention provides an automatic system for visual guidance and navigation using real-time visual anchor point detection, which includes an edge device, a cloud device, and a landmark database; the system of the present invention provides users with navigation directions via visual landmarks. A candidate visual landmark image is selected from the database; the system of the present invention can calculate the time of day, the current weather condition, the current season, etc. In addition, the system of the present invention can use the camera on the dashboard of the vehicle, the camera in the smartphone, or other cameras to collect real-time images; the system of the present invention can also provide feedback on the visibility or salience of landmarks to improve the visual landmark images obtained by subsequent users.

Abstract: A semiconductor die comprises a device portion comprising: an array of active memory devices extending in a first direction, and interface portions located adjacent to axial ends of the device portion in the first direction. The interface portions have a staircase profile in a vertical direction and comprise an array of dummy memory devices and an array of gate vias. The dummy memory devices are axially aligned with the active memory devices in the first direction, each dummy memory device comprising at least one interface via. Moreover, each row of the array of gate vias extends in the first direction and is located parallel to a row of the array of dummy memory devices in a second direction perpendicular to the first direction. Each gate via is electrically coupled to the at least one interface via of a dummy memory device located adjacent thereto.

Abstract: An IC device includes first through third device pairs positioned in first through third active areas extending in a first direction, each pair including first and second transistors coupled between respective first and second anti-fuse structures and a shared bit line contact, and each of the first and third active areas being adjacent to the second active area. First through fourth conductive lines extend in a second direction, first and second conductive paths couple the first conductive line to the first anti-fuse structures, a third conductive path couples the fourth conductive line to the second anti-fuse structures, and a fourth conductive path couples the third conductive line to the second transistors. The first and third conductive paths are aligned along the first direction between the first and second active areas, and the second and fourth conductive paths are aligned along the first direction between the second and third active areas.

Abstract: A one time programmable memory device includes a field effect transistor and an antifuse structure. A first node of the antifuse structure includes, or is electrically connected to, the drain region of the field effect transistor. The antifuse structure includes an antifuse dielectric layer and a second node on, or over, the antifuse dielectric layer. One of the first node and the second node includes the drain region or a metal via structure formed within a via cavity extending through an interlayer dielectric material layer that overlies the field effect transistor.

Abstract: A memory device and a method of operating a memory device are disclosed. In one aspect, the memory device includes a plurality of non-volatile memory cells, each of the plurality of non-volatile memory cells is operatively coupled to a word line, a gate control line, and a bit line. Each of the plurality of non-volatile memory cells comprises a first transistor, a second transistor, a first diode-connected transistor, and a capacitor. The first transistor, second transistor, first diode-connected transistor are coupled in series, with the capacitor having a first terminal connected to a common node between the first diode-connected transistor and the second transistor.

Abstract: A semiconductor memory structure and method of manufacturing a semiconductor memory structure are provided. The semiconductor memory structure includes alternatively arranged stacking portions and cell regions. Each cell region includes two ferroelectric layers formed along the adjacent stacking portions; and at least one central portion disposed between the ferroelectric layers and including a first conductive structure and a second conductive structure separated by a channel isolation structure as well as two semiconductor layers formed along the ferroelectric layers. The first conductive structure includes a contact portion and an extension portion. The contact portion is disposed between the semiconductor layers. The extension portion extends from the contact portion to the channel isolation structure and is separated from the semiconductor layers through dielectric layers.

Abstract: A memory device includes a first layer, wherein the first layer includes a first memory array, a first row decoder circuit, and a first column sensing circuit. The memory device includes a second layer disposed with respect to the first layer in a vertical direction. The second layer includes a first peripheral circuit operatively coupled to the first memory array, the first row decoder circuit, and the first column sensing circuit. The memory device includes a plurality of interconnect structures extending along the vertical direction. At least a first one of the plurality of interconnect structures operatively couples the second layer to the first layer.

Abstract: A memory device includes a first memory block. The first memory block includes a first memory sub-array and a first interface portion disposed next to the first memory sub-array. The first memory block further includes a plurality of first interconnect structures electrically coupled to the first memory sub-array through the first interface portion, and a second plurality of interconnect structures configured to electrically couple a corresponding one of the plurality of first interconnect structures to a transistor. The memory device further includes a first test structure and a second test structure disposed next to the first memory block, each configured to simulate electrical connections of the plurality of second interconnect structures. The first and second test structures are electrically coupled to each other and are each electrically isolated form the first memory block.

Abstract: A memory device includes a first transistor. The first transistor includes one or more first semiconductor nanostructures spaced apart from one another along a first direction. Each of the one or more first semiconductor nanostructures has a first width along a second direction perpendicular to the first direction. The memory device also includes a second transistor coupled to the first transistor in series. The second transistor includes one or more second semiconductor nanostructures spaced apart from one another along the first direction. Each of the one or more second semiconductor nanostructures has a second, different width along the second direction.

Abstract: A memory cell is disclosed. The memory cell includes a first transistor. The first transistor includes a first conduction channel collectively constituted by one or more first nanostructures spaced apart from one another along a vertical direction. The memory cell includes a second transistor electrically coupled to the first transistor in series. The second transistor includes a second conduction channel collectively constituted by one or more second nanostructures spaced apart from one another along the vertical direction. At least one of the one or more first nanostructures is applied with first stress by a first metal structure extending, along the vertical direction, into a first drain/source region of the first transistor.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a fin-based structure formed on a substrate. The semiconductor device includes a plurality of first nanosheets, vertically spaced apart from one another, that are formed on the substrate. The semiconductor device includes a first source/drain (S/D) region electrically coupled to a first end of the fin-based structure. The semiconductor device includes a second S/D region electrically coupled to both of a second end of the fin-based structure and a first end of the plurality of first nanosheets. The semiconductor device includes a third S/D region electrically coupled to a second end of the plurality of first nanosheets. The fin-based structure has a first crystal lattice direction and the plurality of first nano sheets have a second crystal lattice direction, which is different from the first crystal lattice direction.

Abstract: A semiconductor device comprises a source and a pair of drains disposed on either side of the source in a first direction and spaced apart therefrom. A channel layer extending in the first direction is disposed on at least one radially outer surface of the source and the pair of drains in a second direction perpendicular to the first direction. A memory layer extending in the first direction is disposed on a radially outer surface of the channel layer in the second direction. At least one gate layer that extends in the first direction, is disposed on a radially outer surface of the memory layer in the second direction. A gate extension structure extends from the each of the drains at least part way towards the source in the first direction, and is located proximate to, and in contact with each of the channel layer and the corresponding drain.